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4.6Clocks Tab
Figure 9. Clocks Tab
The TLV320AIC3107 provides a phase-locked loop (PLL) that allows flexibility in the clock generation for the ADC and DAC sample rates. The Clocks tab contains the controls that can be used to configure the TLV320AIC3107 for operation with a wide range of master clocks. See the Audio Clock Generation Processing figure in the TLV320AIC3107 data sheet for further details of selecting the correct clock settings.
For use with the PC software and the USB-MODEVM, the clock settings must be set a certain way. If the settings are changed from the default settings which allow operation from the USB-MODEVM clock reference, the EVM settings can be restored automatically by clicking the Load EVM USB Settings button. Note that changing any of the clock settings from the values loaded when this button is pushed can result in the EVM not working properly with the PC software or USB interface. If an external audio bus is used (audio not driven over the USB bus), then settings can be changed to any valid combination. See Figure 9.
4.6.1Configuring the Codec Clocks and Fsref Calculation
The codec clock source is chosen by the CODEC_CLK Source control. When this control is set to CLKDIV_OUT, the PLL is not used; when set to PLLDIV_OUT, the PLL is used to generate the clocks.
Note: Per the TLV320AIC3107 data sheet, the codec must be configured to allow the value of Fsref to fall between the values of 39 kHz to 53 kHz.
SLAU261–November 2008 | TLV320AIC3107EVM-K | 15 |
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