Analog Devices ADSP-BF538F system manual Can Interface on

Page 24

•“CAN Interface” on page 1-11

Describes the on-board Controller Area Network (CAN) interface.

•“ELVIS Interface” on page 1-12

Describes the on-board National Instruments Educational Labora- tory Virtual Instrumentation Suite (NI ELVIS) interface.

•“Audio Interface” on page 1-12Describes the on-board audio circuit.

•“LEDs and Push Buttons” on page 1-13

Describes the board’s general-purpose IO pins and buttons.

•“Example Programs” on page 1-14

Provides information about example programs included in the ADSP-BF538F EZ-KIT Lite evaluation system.

•“Background Telemetry Channel” on page 1-14

Highlights the advantages of the background telemetry channel (BTC) feature of VisualDSP++.

For information on the graphical user interface, including the boot load- ing, target options, and other facilities of the EZ-KIT Lite system, refer to the online Help.

For more detailed information about programming the ADSP-BF538F Blackfin processor, see the documents referred to as “Related Documents”.

1-2

ADSP-BF538F EZ-KIT Lite Evaluation System Manual

Page 23 Page 25
Image 24
Page 23 Page 25
Contents ADSP-BF538F EZ-KIT Lite Evaluation System Manual Limited Warranty Trademark and Service Mark NoticeCopyright Information DisclaimerRegulatory Compliance Page Contents ADSP-BF538F EZ-KIT Lite Hardware Reference ADSP-BF538F EZ-KIT Lite Evaluation System Manual Vii Index Preface Page Preface Page Purpose of This Manual Intended AudienceManual Contents What’s New in This ManualTechnical or Customer Support Supported ProcessorsProduct Information MyAnalog.comProcessor Product Information Related Documents Title DescriptionOnline Technical Documentation Related VisualDSP++ PublicationsAccessing Documentation From VisualDSP++ Accessing Documentation From Web Printed ManualsNotation Conventions Example DescriptionNotation Conventions Using ADSP-BF538F EZ-KIT Lite Can Interface on Package Contents Default ConfigurationDefault Configuration Installation and Session Startup Installation and Session Startup Evaluation License Restrictions Memory MapSdram Interface Sdram InterfaceRegister Value Function Flash Memory Flash MemoryCan Interface Elvis Interface Audio InterfaceLEDs and Push Buttons Example Programs Background Telemetry ChannelADSP-BF538F EZ-KIT Lite Hardware Reference System Architecture DSPExternal Bus Interface Unit ADSP-BF538F EZ-KIT Lite Hardware ReferenceSPORT0 Interface SPI InterfaceUart Interface Programmable FlagsProgrammable Flag Connections Cont’d Ppidirctl for AV-Extender Flag Push Buttons SW10-13 on Uart Port Expansion InterfaceJumper and Switch Settings Jtag Emulation PortCan Enable Switch SW2 Uart Enable Switch SW4Push Button Enable Switch SW5 Flash Enable Switch SW6FCE Enable Switch SW14 Audio Enable Switch SW7Boot Mode Select Switch SW3 PPI Direction Control JP1Elvis Oscilloscope Configuration Switch SW1 Uart Loop Jumper JP9Elvis Function Generator Configuration Switch SW8 Channel SW8 Switch Position Default Audio Circuit SignalElvis Voltage Selection Jumper JP6 Elvis Select Jumper JP8Reset Push Button SW9 LED and Push Button LocationsPower LED LED7 Reset LED LED8Programmable Flag Push Buttons SW10-13 User LEDs LED2-6 USB Monitor LED ZLED3Connectors Audio Connectors J9 and J10 Can Connectors J5 and J11RS-232 Connector J6 Power Connector J7 Expansion Interface Connectors J1-3Jtag Connector ZP4 SPORT0 and SPORT1 Connectors P6 and P7PPI Connector P8 SPI Connector P9 Wire Interface Connector P10Timers Connector P11 UART1 Connector P12 Connectors ADSP-BF538F EZ-KIT Lite Bill of Materials FDS6990AS SOIC8 ADSP-BF538F EZ-KIT Lite Bill Of Materials CT7 AVX Vishay CRCW04024K70JNED Vishay CRCW060310K0JNEA Panasonic ERJ-3RSFR10V Panasonic ECJ-1VB1H222K ADSP-BF538F EZ-KIT Lite Schematic ADSP-BF538F EZ-KIT Lite TitleADSP-BF538F EZ-KIT Lite DSPRTC ADSP-BF538F EZ-KIT Lite DSP Power VddextMB Sdram ADSP-BF538F EZ-KIT Lite Sdram and FlashADC ADSP-BF538F EZ-KIT Lite ADC and AudioDAC ADSP-BF538F EZ-KIT Lite DAC and Audio OUTCan Sheet 7ADSP-BF538F EZ-KIT Lite Push BUTTONS, Leds and Boot Mode Jumperelvis Connector DSP Core Voltage & CurrentPFI DSP IO CurrentExpansion Interface Type B DSP Jtag HeaderTimers Uart ADSP-BF538F EZ-KIT Lite Stamp ConnectorsSport Serial PortADSP-BF538F EZ-KIT Lite Misc Connectors ADSP-BF538F EZ-KIT Lite Power LabelIndex Index PPI SPI Uart Page Processors White Papers Technical Support Page Log MyAnalog Sharc Processor Leadership in Mflops per $ Performance Learning and Development Technical Library Page Blackfin Processor Development Tools Development Tools Support

ADSP-BF538F specifications

The Analog Devices ADSP-BF538F is a high-performance Blackfin processor that stands out in the realm of digital signal processing. This processor is designed specifically for applications that require intensive signal processing, such as audio and video encoding/decoding, industrial automation, and medical imaging. Its combination of processing power, low power consumption, and rich feature set makes it an ideal choice for embedded systems.

One of the main features of the ADSP-BF538F is its dual-core architecture, which allows for simultaneous execution of multiple threads. This architecture leverages the strengths of both RISC and SIMD (Single Instruction, Multiple Data) processing, enabling it to handle complex algorithms effectively. Additionally, the processor operates at clock speeds of up to 600 MHz, delivering impressive performance while maintaining energy efficiency.

Technologically, the ADSP-BF538F incorporates a diverse range of peripherals that enhance its versatility. It features integrated multimedia capabilities, including a video port for interfacing with cameras and displays, and a direct memory access (DMA) controller that facilitates rapid data transfer between memory and peripherals. This efficient data handling is critical in applications where real-time performance is essential.

The processor is equipped with rich memory resources, including up to 1 MB of on-chip SRAM and an external memory interface that supports various memory types, such as SDRAM and Flash. This ample memory capacity is crucial for application scenarios that require high-speed data processing and storage.

Power management is another key characteristic of the ADSP-BF538F. It features multiple power-saving modes that allow developers to optimize for energy efficiency without sacrificing performance. This makes it suitable for battery-operated devices where power consumption is a crucial consideration.

Furthermore, the ADSP-BF538F is designed with a development-friendly ecosystem, supporting various development tools and software. The processor is compatible with the VisualDSP++ development environment, which provides a comprehensive suite of application development tools, making it accessible for engineers to implement their projects efficiently.

In summary, the Analog Devices ADSP-BF538F is a cutting-edge signal processing solution that combines high-performance capabilities with energy efficiency. Its dual-core architecture, extensive peripherals, rich memory resources, and robust development support make it a powerful choice for a wide range of embedded applications. Whether in industrial, automotive, or consumer electronics, the ADSP-BF538F is poised to deliver outstanding performance and reliability.
Top Page Image Contents