Analog Devices ADSP-BF538F system manual Index

Page 85

INDEX

connectors

diagram of locations, 2-20

J1-3 (expansion), 2-3, 2-8, 2-22J5 and J11 (CAN), 2-21

J6 (RS-232), 2-21

J7 (power), 2-22

J9-10 (audio), 2-21

P10 (TWI), 2-24

P11 (timers), 2-24

P12 (UART1), 2-25

P3 (SPORT1), 2-4

P4 (SPORT2), 2-4

P6 (SPORT0), 1-13,2-4,2-23P8 (PPI), 2-23

P9 (SPI), 2-4, 2-24SPORT0-1 (P6-7), 2-23ZP4 (JTAG), 2-9, 2-23

contents, of this EZ-KIT Lite package, 1-3Controller Area Network, See CAN

core voltage, 2-2CTS signals, 2-10customer support, xv

E

EBIU_SDBCTL register, 1-9, 1-10EBIU_SDGCTL register, 1-9,1-10EBIU_SDRRC register, 1-9, 1-10EBUI control signals, 2-8Educational Laboratory Virtual

Instrumentation Suite interface, See ELVIS ELVIS

interface, xi, 1-12, 2-14select jumper (JP8), 2-16voltage select jumper (JP6), 2-16

ELVIS_PF1-2 signals, 2-5ELVIS_PF5-7 signals, 2-5

EN (enable control input) signals, 2-10ERR signals, 1-11, 2-6, 2-10example programs, 1-14

expansion interface connections, 1-13, 2-3, 2-4, 2-11connectors (J1-3), 2-8, 2-22

external bus interface unit (EBIU), 2-3external memory, 1-8,2-3, 2-9

D

DAC1-0 signals, 2-15

data acquisition (DAQ) device, 1-12DB9 (UART) connector, xii, 2-8

default configuration, of this EZ-KIT Lite, 1-3DIP switch (SW5), 1-4, 1-13

DR0PRI signals, 2-12DR2PRI signal, 2-6DR2SEC signal, 2-6DR3PRI signal, 2-6DR3SEC signal, 2-6DT2PRI signal, 2-6DT2SEC signal, 2-6DT3PRI signal, 2-6DT3SEC signal, 2-6

F

FCE enable switch (SW14), 2-12features, of this EZ-KIT Lite, xi flag pins, See programmable flags flash memory

boot mode, 2-13connections, 2-3

enable switch (SW6), 1-10, 2-11frame sync signals, 1-13frequency, 1-9

FS loopback signal, 2-13FUNCT_OUT signal, 2-15

G

general-purpose IO pins, 1-13, 2-10, 2-11, 2-19GND signal, 2-8

I-2

ADSP-BF538F EZ-KIT Lite Evaluation System Manual

Page 84 Page 86
Image 85
Page 84 Page 86
Contents ADSP-BF538F EZ-KIT Lite Evaluation System Manual Trademark and Service Mark Notice Limited WarrantyCopyright Information DisclaimerRegulatory Compliance Page Contents ADSP-BF538F EZ-KIT Lite Hardware Reference ADSP-BF538F EZ-KIT Lite Evaluation System Manual Vii Index Preface Page Preface Page Intended Audience Purpose of This ManualWhat’s New in This Manual Manual ContentsSupported Processors Technical or Customer SupportMyAnalog.com Product InformationProcessor Product Information Title Description Related DocumentsRelated VisualDSP++ Publications Online Technical DocumentationAccessing Documentation From VisualDSP++ Printed Manuals Accessing Documentation From WebExample Description Notation ConventionsNotation Conventions Using ADSP-BF538F EZ-KIT Lite Can Interface on Default Configuration Package ContentsDefault Configuration Installation and Session Startup Installation and Session Startup Memory Map Evaluation License RestrictionsSdram Interface Sdram InterfaceRegister Value Function Flash Memory Flash MemoryCan Interface Audio Interface Elvis InterfaceLEDs and Push Buttons Background Telemetry Channel Example ProgramsADSP-BF538F EZ-KIT Lite Hardware Reference DSP System ArchitectureADSP-BF538F EZ-KIT Lite Hardware Reference External Bus Interface UnitSPI Interface SPORT0 InterfaceUart Interface Programmable FlagsProgrammable Flag Connections Cont’d Ppidirctl for AV-Extender Flag Push Buttons SW10-13 on Expansion Interface Uart PortJtag Emulation Port Jumper and Switch SettingsUart Enable Switch SW4 Can Enable Switch SW2Flash Enable Switch SW6 Push Button Enable Switch SW5Audio Enable Switch SW7 FCE Enable Switch SW14PPI Direction Control JP1 Boot Mode Select Switch SW3Uart Loop Jumper JP9 Elvis Oscilloscope Configuration Switch SW1Channel SW8 Switch Position Default Audio Circuit Signal Elvis Function Generator Configuration Switch SW8Elvis Select Jumper JP8 Elvis Voltage Selection Jumper JP6LED and Push Button Locations Reset Push Button SW9Reset LED LED8 Power LED LED7Programmable Flag Push Buttons SW10-13 USB Monitor LED ZLED3 User LEDs LED2-6Connectors Can Connectors J5 and J11 Audio Connectors J9 and J10RS-232 Connector J6 Expansion Interface Connectors J1-3 Power Connector J7SPORT0 and SPORT1 Connectors P6 and P7 Jtag Connector ZP4PPI Connector P8 Wire Interface Connector P10 SPI Connector P9Timers Connector P11 UART1 Connector P12 Connectors ADSP-BF538F EZ-KIT Lite Bill of Materials FDS6990AS SOIC8 ADSP-BF538F EZ-KIT Lite Bill Of Materials CT7 AVX Vishay CRCW04024K70JNED Vishay CRCW060310K0JNEA Panasonic ERJ-3RSFR10V Panasonic ECJ-1VB1H222K ADSP-BF538F EZ-KIT Lite Title ADSP-BF538F EZ-KIT Lite SchematicDSP ADSP-BF538F EZ-KIT LiteRTC Vddext ADSP-BF538F EZ-KIT Lite DSP PowerADSP-BF538F EZ-KIT Lite Sdram and Flash MB SdramADSP-BF538F EZ-KIT Lite ADC and Audio ADCADSP-BF538F EZ-KIT Lite DAC and Audio OUT DACSheet 7 CanADSP-BF538F EZ-KIT Lite Push BUTTONS, Leds and Boot Mode DSP Core Voltage & Current Jumperelvis ConnectorPFI DSP IO CurrentDSP Jtag Header Expansion Interface Type BADSP-BF538F EZ-KIT Lite Stamp Connectors Timers UartSport Serial PortADSP-BF538F EZ-KIT Lite Misc Connectors Label ADSP-BF538F EZ-KIT Lite PowerIndex Index PPI SPI Uart Page Processors White Papers Technical Support Page Log MyAnalog Sharc Processor Leadership in Mflops per $ Performance Learning and Development Technical Library Page Blackfin Processor Development Tools Development Tools Support

ADSP-BF538F specifications

The Analog Devices ADSP-BF538F is a high-performance Blackfin processor that stands out in the realm of digital signal processing. This processor is designed specifically for applications that require intensive signal processing, such as audio and video encoding/decoding, industrial automation, and medical imaging. Its combination of processing power, low power consumption, and rich feature set makes it an ideal choice for embedded systems.

One of the main features of the ADSP-BF538F is its dual-core architecture, which allows for simultaneous execution of multiple threads. This architecture leverages the strengths of both RISC and SIMD (Single Instruction, Multiple Data) processing, enabling it to handle complex algorithms effectively. Additionally, the processor operates at clock speeds of up to 600 MHz, delivering impressive performance while maintaining energy efficiency.

Technologically, the ADSP-BF538F incorporates a diverse range of peripherals that enhance its versatility. It features integrated multimedia capabilities, including a video port for interfacing with cameras and displays, and a direct memory access (DMA) controller that facilitates rapid data transfer between memory and peripherals. This efficient data handling is critical in applications where real-time performance is essential.

The processor is equipped with rich memory resources, including up to 1 MB of on-chip SRAM and an external memory interface that supports various memory types, such as SDRAM and Flash. This ample memory capacity is crucial for application scenarios that require high-speed data processing and storage.

Power management is another key characteristic of the ADSP-BF538F. It features multiple power-saving modes that allow developers to optimize for energy efficiency without sacrificing performance. This makes it suitable for battery-operated devices where power consumption is a crucial consideration.

Furthermore, the ADSP-BF538F is designed with a development-friendly ecosystem, supporting various development tools and software. The processor is compatible with the VisualDSP++ development environment, which provides a comprehensive suite of application development tools, making it accessible for engineers to implement their projects efficiently.

In summary, the Analog Devices ADSP-BF538F is a cutting-edge signal processing solution that combines high-performance capabilities with energy efficiency. Its dual-core architecture, extensive peripherals, rich memory resources, and robust development support make it a powerful choice for a wide range of embedded applications. Whether in industrial, automotive, or consumer electronics, the ADSP-BF538F is poised to deliver outstanding performance and reliability.
Top Page Image Contents