Analog Devices ADSP-BF538F system manual LEDs and Push Buttons

Page 35

Using ADSP-BF538F EZ-KIT Lite

The frame sync and bit clocks are generated from the ADC and feed to the processor because the ADC is operating in master mode. The audio inter- face samples data at a 48 kHz sample rate. The serial data interface operates in 2-wire interface (TWI) mode and connects to SPORT0 of the processor.

The audio interface can be disconnected from the SPORT0 by turning positions 1 and 5 of the SW7 switch OFF. When in the OFF position, the SPORT0 signals can be used on the SPORT0 connector (P6) or on the expan- sion interface (see “SPORT0 and SPORT1 Connectors (P6 and P7)” on page 2-23and “Audio Enable Switch (SW7)” on page 2-12for more information).

Example programs are included in the EZ-KIT Lite installation directory to demonstrate audio circuit operation.

LEDs and Push Buttons

The EZ-KIT Lite provides four push buttons and five LEDs for gen- eral-purpose IO.

The five LEDs, labeled LED2 through LED6, are accessed via the PC5–9pro- cessor pins. For information on how to program the pins, refer to the ADSP-BF538/ADSP-BF538F Blackfin Processor Hardware Reference.

The four general-purpose push button are labeled SW10 through SW13. A status of each individual button can be read through the processor’s pro- grammable flag inputs, PF0–3. The signal reads 1 when a corresponding switch is being pressed-on. When the switch is released, the signal reads 0. A connection between the push button and programmable flag input is established through the DIP switch, SW5. See “LEDs and Push Buttons” on page 2-17for details.

An example program is included in the EZ-KIT Lite installation directory to demonstrate functionality of the LEDs and push buttons.

ADSP-BF538F EZ-KIT Lite Evaluation System Manual

1-13

Page 34 Page 36
Image 35
Page 34 Page 36
Contents ADSP-BF538F EZ-KIT Lite Evaluation System Manual Disclaimer Limited WarrantyTrademark and Service Mark Notice Copyright InformationRegulatory Compliance Page Contents ADSP-BF538F EZ-KIT Lite Hardware Reference ADSP-BF538F EZ-KIT Lite Evaluation System Manual Vii Index Preface Page Preface Page Intended Audience Purpose of This ManualWhat’s New in This Manual Manual ContentsSupported Processors Technical or Customer SupportProcessor Product Information Product InformationMyAnalog.com Title Description Related DocumentsRelated VisualDSP++ Publications Online Technical DocumentationAccessing Documentation From VisualDSP++ Printed Manuals Accessing Documentation From WebExample Description Notation ConventionsNotation Conventions Using ADSP-BF538F EZ-KIT Lite Can Interface on Default Configuration Package ContentsDefault Configuration Installation and Session Startup Installation and Session Startup Memory Map Evaluation License RestrictionsSdram Interface Sdram InterfaceRegister Value Function Flash Memory Flash MemoryCan Interface Audio Interface Elvis InterfaceLEDs and Push Buttons Background Telemetry Channel Example ProgramsADSP-BF538F EZ-KIT Lite Hardware Reference DSP System ArchitectureADSP-BF538F EZ-KIT Lite Hardware Reference External Bus Interface UnitProgrammable Flags SPORT0 InterfaceSPI Interface Uart InterfaceProgrammable Flag Connections Cont’d Ppidirctl for AV-Extender Flag Push Buttons SW10-13 on Expansion Interface Uart PortJtag Emulation Port Jumper and Switch SettingsUart Enable Switch SW4 Can Enable Switch SW2Flash Enable Switch SW6 Push Button Enable Switch SW5Audio Enable Switch SW7 FCE Enable Switch SW14PPI Direction Control JP1 Boot Mode Select Switch SW3Uart Loop Jumper JP9 Elvis Oscilloscope Configuration Switch SW1Channel SW8 Switch Position Default Audio Circuit Signal Elvis Function Generator Configuration Switch SW8Elvis Select Jumper JP8 Elvis Voltage Selection Jumper JP6LED and Push Button Locations Reset Push Button SW9Programmable Flag Push Buttons SW10-13 Power LED LED7Reset LED LED8 USB Monitor LED ZLED3 User LEDs LED2-6Connectors RS-232 Connector J6 Audio Connectors J9 and J10Can Connectors J5 and J11 Expansion Interface Connectors J1-3 Power Connector J7PPI Connector P8 Jtag Connector ZP4SPORT0 and SPORT1 Connectors P6 and P7 Timers Connector P11 SPI Connector P9Wire Interface Connector P10 UART1 Connector P12 Connectors ADSP-BF538F EZ-KIT Lite Bill of Materials FDS6990AS SOIC8 ADSP-BF538F EZ-KIT Lite Bill Of Materials CT7 AVX Vishay CRCW04024K70JNED Vishay CRCW060310K0JNEA Panasonic ERJ-3RSFR10V Panasonic ECJ-1VB1H222K ADSP-BF538F EZ-KIT Lite Title ADSP-BF538F EZ-KIT Lite SchematicRTC ADSP-BF538F EZ-KIT LiteDSP Vddext ADSP-BF538F EZ-KIT Lite DSP PowerADSP-BF538F EZ-KIT Lite Sdram and Flash MB SdramADSP-BF538F EZ-KIT Lite ADC and Audio ADCADSP-BF538F EZ-KIT Lite DAC and Audio OUT DACSheet 7 CanADSP-BF538F EZ-KIT Lite Push BUTTONS, Leds and Boot Mode DSP IO Current Jumperelvis ConnectorDSP Core Voltage & Current PFIDSP Jtag Header Expansion Interface Type BSerial Port Timers UartADSP-BF538F EZ-KIT Lite Stamp Connectors SportADSP-BF538F EZ-KIT Lite Misc Connectors Label ADSP-BF538F EZ-KIT Lite PowerIndex Index PPI SPI Uart Page Processors White Papers Technical Support Page Log MyAnalog Sharc Processor Leadership in Mflops per $ Performance Learning and Development Technical Library Page Blackfin Processor Development Tools Development Tools Support

ADSP-BF538F specifications

The Analog Devices ADSP-BF538F is a high-performance Blackfin processor that stands out in the realm of digital signal processing. This processor is designed specifically for applications that require intensive signal processing, such as audio and video encoding/decoding, industrial automation, and medical imaging. Its combination of processing power, low power consumption, and rich feature set makes it an ideal choice for embedded systems.

One of the main features of the ADSP-BF538F is its dual-core architecture, which allows for simultaneous execution of multiple threads. This architecture leverages the strengths of both RISC and SIMD (Single Instruction, Multiple Data) processing, enabling it to handle complex algorithms effectively. Additionally, the processor operates at clock speeds of up to 600 MHz, delivering impressive performance while maintaining energy efficiency.

Technologically, the ADSP-BF538F incorporates a diverse range of peripherals that enhance its versatility. It features integrated multimedia capabilities, including a video port for interfacing with cameras and displays, and a direct memory access (DMA) controller that facilitates rapid data transfer between memory and peripherals. This efficient data handling is critical in applications where real-time performance is essential.

The processor is equipped with rich memory resources, including up to 1 MB of on-chip SRAM and an external memory interface that supports various memory types, such as SDRAM and Flash. This ample memory capacity is crucial for application scenarios that require high-speed data processing and storage.

Power management is another key characteristic of the ADSP-BF538F. It features multiple power-saving modes that allow developers to optimize for energy efficiency without sacrificing performance. This makes it suitable for battery-operated devices where power consumption is a crucial consideration.

Furthermore, the ADSP-BF538F is designed with a development-friendly ecosystem, supporting various development tools and software. The processor is compatible with the VisualDSP++ development environment, which provides a comprehensive suite of application development tools, making it accessible for engineers to implement their projects efficiently.

In summary, the Analog Devices ADSP-BF538F is a cutting-edge signal processing solution that combines high-performance capabilities with energy efficiency. Its dual-core architecture, extensive peripherals, rich memory resources, and robust development support make it a powerful choice for a wide range of embedded applications. Whether in industrial, automotive, or consumer electronics, the ADSP-BF538F is poised to deliver outstanding performance and reliability.
Top Page Image Contents