Chapter 1: Introduction
1-2 Chipset and Processor Features Overview
Built upon the functionality and the capability of the Intel 5100 chipset, the X7DCL-
The 5100 Memory Controller Hub (MCH)
The Intel 5100 MCH chip is designed for symmetric multiprocessing across two independent front side bus interfaces. Each front side bus uses a
The 5100 MCH also provides six x4
The Ninth Generation I/O Controller Hub (ICH9)
The I/O Controller ICH9R provides the data buffering and interface arbitration required for the system to operate efficiently. It also provides the bandwidth needed for the system to maintain its peak performance. The Direct Media Interface (DMI) provides the connection between the MCH and the ICH9R. The ICH9R supports up to six