NXP Semiconductors | UM10301 |
| User Manual PCF85x3, PCA8565 and PCF2123, PCA2125 |
As an example, the desired timer period is 5 seconds. If the timer source clock frequency is set to 1 Hz and n = 5, the minimum possible timer period will be
Similarly, if the desired timer delay is 1 minute, one option would be to chose the timer source clock 1/60 Hz and set n = 1. However, then there would be only one timer period and it has an uncertainty. The duration is not exactly defined. A better way is to select the 1 Hz source clock and set n = 60. There will be an uncertainty in the first period too but the consecutive 59 periods are exact and the resulting total uncertainty is 60 times smaller.
The conclusion is that for a given desired delay, minimum uncertainty will be achieved by choosing a higher setting of n combined with a higher timer source clock.
At the end of every count down the timer sets the Timer Flag (TF). The TF may only be cleared by software. The asserted TF can be used to generate an interrupt signal on pin INT provided that this mode is enabled. Refer to the relevant datasheet for details on how the interrupt can be controlled which is done via certain bits in the control registers. The timer has two operating modes, TI and TP. If the timer interrupt is enabled, the bit TI/TP determines the operating mode. If bit TI_TP is set to 1, the chosen timer mode is ‘pulsed’. In this mode an interrupt is generated after the timer period elapses. This is independent of the timer flag and will thus happen every time the timer periode elapses, periodically. The clearing of the timer flag is only necessary if TI mode is chosen, if the consecutive interrupt is to happen. In the TI mode the signal remains permanently high as long as the Timer Flag is active.
18. Timing requirements for I2C read and write
Reading to and writing from the time and date registers is an event which is controlled by the interface bus (I2C or SPI) but which is asynchronous to the internal 32.768 kHz clock of the RTC. It happens at random instants with respect to the automatic update of the internal registers. Without precautions, two types of read errors could occur when the time and date registers increment while being read. First, the data could change while a single register is being read. Second, the data could change during the time between reading two registers. Assume for example that the clock increments from 09:59:59 to 10:00:00 during a read of the seconds, minutes and hours registers. The time read could be 10:00:59 and this is incorrect. A similar reasoning applies to writing. Measures must be taken to prevent such read and write errors. In the NXP RTCs this is realized by freezing the contents of all counters when one of the RTC registers is read or written. This is called time counter freeze. Therefore faulty reading of the clock/calendar during a carry condition is prevented.
Fig 10 shows the block diagram of the PCF8563 with attached to the
UM10301_1 |
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User manual | Rev. 01 — 23 December 2008 | 45 of 52 |