NXP Semiconductors PCF2123, PCF85x3, PCA8565 Voltage-low detection, Oscillator-stop detection

Page 9

NXP Semiconductors

UM10301

 

User Manual PCF85x3, PCA8565 and PCF2123, PCA2125

The implementation in the PCF2123 is slightly different. There a bit OS (Oscillator Stopped) is present instead of VL. The OS flag is set whenever the oscillator is stopped, and therefore also when this is due to the supply voltage dropping too low. The flag can only be cleared by software and only if the oscillator is running again.

 

mgr887

VDD

 

 

normal power

 

operation

period of battery

 

operation

 

Vlow

 

VL set

t

 

VDD

VOSC(MIN)

Main supply

Battery operation

t

<OS>

(1) Valid for PCF8563 and PCA8565

Fig 2. Voltage-low detection

(2) Valid for PCF2123

Fig 3. Oscillator-stop detection

In the case of PCF8563/PCA8565 bit VL set indicates that the integrity of the clock information is no longer guaranteed. If the oscillator hasn’t stopped, the clock information will still be ok, but with VDD having dropped below Vlow there is no guarantee that this still is the case because there is no way to be sure that the oscillator kept running. The VL flag can only be cleared by software.

Both VL and OS are intended to detect the situation when VDD is decreasing slowly, for example under battery operation. Should VDD reach the limit where the flag is set before power is re-asserted, then the flag VL or OS will indicate that time may be (VL) or is (OS)

corrupted. VDD dropping below Vlow or Vosc(min) in itself does not cause any register to be reset. Once the oscillator stops some registers will be reset.

6. Oscillator

A crystal oscillator as used in a real-time clock, see Fig 4, is built on the principle of Pierce and uses an inverting amplifier with a crystal in the feedback path and load capacitors CIN and COUT to provide the necessary additional phase shift. Some phase shift is contributed as a result of the amplifier’s non-zero output impedance in combination with COUT. The oscillator operates at the frequency for which the crystal is anti-resonant (i.e. parallel resonant) with the total capacitive load of the oscillating circuit as seen from the pins of the crystal. This total capacitance is called the load capacitance.

The load capacitance is defined as the capacitance seen from the pins of the crystal and

is formed by CIN, COUT and CSTRAY indicated in Fig 4. Electrically the crystal’s C0 is also a load capacitance which affects oscillator characteristics. However, it is not part of the

defined ‘load capacitance’. During manufacturing the crystal is tuned to the specified frequency with a specified load capacitance connected to the crystal. Since C0 is part of the crystal, it is automatically taken into account during the adjustment procedure.

UM10301_1

 

© NXP B.V. 2008. All rights reserved.

User manual

Rev. 01 — 23 December 2008

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Contents Info Content Keywords Document informationAbstract NXP Semiconductors Contact informationRevision history Rev Date DescriptionIntroduction Features Address Register name Bit Register overview PCF8563Comparison Event counter modeComparison of six real time clocks FeaturesPower-on reset POR Power-on resetVoltage-low detector Oscillator Voltage-low detectionOscillator-stop detection Overview of internal and external oscillator capacitors Pierce Oscillator equivalent diagramOscillator frequency determining components UM10301 + C Parameter Value Unit Source Typical values for crystal and surrounding capacitorsOscillation allowance Using an external oscillatorCrystal and crystal selection Modes which don’t work Effect of temperature− f nom Capacitors and capacitor selection Accuracy Influences on time accuracy Oscillator tuning Oscillator tuning 10.1 PCF2123 Offset register Century tracking Century and leap year, Daylight Saving TimeYear and leap year tracking Daylight Saving Time DSTInitialization and setting of alarm and timer Initialization of the RTC and setting the timeBlock Diagram PCF8563 Setting the alarm AlarmBinary BCD Register Comments AddressAlarm function Setting the timer Setting the timerRegister Lithium Primary cells Backup power supplyBackup circuit using primary lithium cell NiCd and NiMH secondary batteries Backup circuit using secondary cell NiCd or NiMH13.3 Capacitors Charging the backup capacitor Some suggestions for diode D1 Diode selection1N4148 BAS716 BAS116 BAV170PCB layout guidelines PCB layout proposal for PCF8563 using leaded components Partial circuit switch down Protection diodes Hints to keep power consumption low0007 Rpmax as a function of bus capacitance 8473 ⋅ C bApplication diagram 2, SPI interface Application diagram 1, I2C-bus interfaceTimer delays First period inaccuracy when using the timerTimer Source clock frequency Delay for n = General countdown timer behaviourTimer source clock Minimum timer period Maximum timer period First period delay for timer counter value nTiming requirements for I2C read and write I2C interface Block diagram I2C interface and Time countersSequence of events example Read Oscillator startup time Checking for oscillation TroubleshootingNo communication via I2C-bus Wrong time and date, wrong clock speed ReferencesDefinitions Legal informationDisclaimers TrademarksContents
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