NXP Semiconductors PCF85x3, PCF2123, PCA8565, PCA2125 Power-on reset POR, Voltage-low detector

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NXP Semiconductors

UM10301

 

User Manual PCF85x3, PCA8565 and PCF2123, PCA2125

4. Power-on reset (POR)

Traditionally a power-on reset circuit is a circuit that generates a reset pulse once the supply voltage has reached a certain value upon power-up. The purpose is to ensure a defined behavior at start-up. This type of power-on reset is not present in these RTCs.

The power-on reset circuit (POR) for these RTCs does not look at the supply voltage, but instead it is based on an internal reset circuit which is active whenever the oscillator is stopped, refer to Fig 1. When power is applied to the device it will take some time for the oscillator to start and during this time the circuit will generate a reset. Also when during operation the OSCI- or OSCO-pin is pulled to ground, causing oscillation to stop, the POR will generate a reset pulse. In the reset state the serial bus logic is initialized and all registers are reset according to the register reset values. Not all registers will be reset. The only registers that are reset are the ones that control a function i.e. decide on clock mode, enable an alarm etc. Refer to the datasheet of the respective device for details.

The power on reset duration is thus directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits on-board testing of the device would take longer too. In order to speed up this, a mechanism has been built in to disable the POR (not for PCF8583, PCF8593 and PCF2123). This is called Power- on reset override. Again, refer to the respective datasheet for details. Once the override mode has been entered, the device stops immediately being reset and set-up operation e.g. entry into the external clock test mode, may commence via the serial interface.

chip in reset

VDD

oscillation

internal reset

chip not in reset

t

001aaf897

Fig 1. Power-on reset

5. Voltage-low detector

PCF8563, PCA8565 and PCF2123 have an on-chip voltage-low detector, see Fig 2 and Fig 3. When VDD drops below a certain limit defined as Vlow, bit VL in the seconds register of PCF8563 and PCA8565 is set. Generally the VL-bit is intended to indicate that the time might be wrong, not that it necessarely is wrong. It will be set if one of the following four conditions occur:

•The power has just been applied;

•The power has dipped down and then recovered;

•The power has gone away and then come back again;

•When the oscillator stops running.

UM10301_1

 

© NXP B.V. 2008. All rights reserved.

User manual

Rev. 01 — 23 December 2008

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Contents Abstract Info Content KeywordsDocument information Contact information NXP SemiconductorsRevision history Rev Date DescriptionIntroduction Features Register overview PCF8563 Address Register name BitEvent counter mode ComparisonFeatures Comparison of six real time clocksVoltage-low detector Power-on reset PORPower-on reset Oscillator-stop detection OscillatorVoltage-low detection Pierce Oscillator equivalent diagram Overview of internal and external oscillator capacitorsOscillator frequency determining components UM10301 + C Typical values for crystal and surrounding capacitors Parameter Value Unit SourceUsing an external oscillator Oscillation allowanceCrystal and crystal selection Effect of temperature Modes which don’t work− f nom Capacitors and capacitor selection Accuracy Influences on time accuracy Oscillator tuning Oscillator tuning 10.1 PCF2123 Offset register Century and leap year, Daylight Saving Time Century trackingYear and leap year tracking Daylight Saving Time DSTBlock Diagram PCF8563 Initialization and setting of alarm and timerInitialization of the RTC and setting the time Alarm Setting the alarmBinary BCD Register Comments AddressAlarm function Register Setting the timerSetting the timer Backup power supply Lithium Primary cellsBackup circuit using primary lithium cell Backup circuit using secondary cell NiCd or NiMH NiCd and NiMH secondary batteries13.3 Capacitors Charging the backup capacitor Diode selection Some suggestions for diode D11N4148 BAS716 BAS116 BAV170PCB layout guidelines PCB layout proposal for PCF8563 using leaded components Partial circuit switch down Hints to keep power consumption low Protection diodes0007 8473 ⋅ C b Rpmax as a function of bus capacitanceApplication diagram 1, I2C-bus interface Application diagram 2, SPI interfaceFirst period inaccuracy when using the timer Timer delaysTimer Source clock frequency Delay for n = General countdown timer behaviourFirst period delay for timer counter value n Timer source clock Minimum timer period Maximum timer periodTiming requirements for I2C read and write Block diagram I2C interface and Time counters I2C interfaceSequence of events example Read Troubleshooting Oscillator startup time Checking for oscillationNo communication via I2C-bus References Wrong time and date, wrong clock speedLegal information DefinitionsDisclaimers TrademarksContents
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