STK17TA8
MODE Selection
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| E |
| W |
| G |
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| Mode | I/O | Power | Notes | ||
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H |
| X |
| X |
| X | Not Selected | Output High Z | Standby |
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| L |
| H |
| L |
| X | Read SRAM | Output Data | Active |
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| L |
| L |
| X |
| X | Write SRAM | Input Data | Active |
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| L |
| H |
| L |
| 0x04E38 | Read SRAM | Output Data |
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| 0x0B1C7 | Read SRAM | Output Data |
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| 0x083E0 | Read SRAM | Output Data | Active | 17, 18, 19 |
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| 0x07C1F | Read SRAM | Output Data |
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| 0x0703F | Read SRAM | Output Data |
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| 0x08FC0 | Nonvolatile Store | Output High Z | ICC2 |
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| H |
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| 0x04E38 | Read SRAM | Output Data | Active |
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| 0x0B1C7 | Read SRAM | Output Data |
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| 0x083E0 | Read SRAM | Output Data |
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| 0x07C1F | Read SRAM | Output Data |
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| 0x0703F | Read SRAM | Output Data |
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| 0x04C63 | Nonvolatile Recall | Output High Z |
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Notes
17.The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
18.While there are 17 addresses on the STK17TA8, only the lower 16 are used to control software modes
19.I/O state depends on the state of G. The I/O table shown assumes G low
Document #: | Page 11 of 23 |
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