Cypress STK17TA8 manual Mode Selection, A16-A0 Mode Power

Page 11

STK17TA8

MODE Selection

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

W

 

G

 

A16-A0

Mode

I/O

Power

Notes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

X

 

X

 

X

Not Selected

Output High Z

Standby

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

H

 

L

 

X

Read SRAM

Output Data

Active

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

 

X

 

X

Write SRAM

Input Data

Active

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

H

 

L

 

0x04E38

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

0x0B1C7

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

0x083E0

Read SRAM

Output Data

Active

17, 18, 19

 

 

 

 

 

 

 

 

 

0x07C1F

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

0x0703F

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

0x08FC0

Nonvolatile Store

Output High Z

ICC2

 

 

L

 

H

 

L

 

0x04E38

Read SRAM

Output Data

Active

 

 

 

 

 

 

 

 

 

 

0x0B1C7

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

0x083E0

Read SRAM

Output Data

 

17, 18, 19

 

 

 

 

 

 

 

 

 

0x07C1F

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

0x0703F

Read SRAM

Output Data

 

 

 

 

 

 

 

 

 

 

 

0x04C63

Nonvolatile Recall

Output High Z

 

 

Notes

17.The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.

18.While there are 17 addresses on the STK17TA8, only the lower 16 are used to control software modes

19.I/O state depends on the state of G. The I/O table shown assumes G low

Document #: 001-52039 Rev. **

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram DescriptionPin Descriptions PinoutsAbsolute Maximum Ratings DC Electrical CharacteristicsRF SSOP-48 Package Thermal Characteristics Symbol Parameter Commercial Industrial Units MinCapacitance Symbol Parameter Commercial Industrial Units Min MaxSymbol Parameter Max Units Conditions AC Test ConditionsRTC DC Characteristics Sram Read Cycles #1 and #2 Symbols Parameter STK17TA8-25 STK17TA8-45 Units Alt Min MaxSram Write Cycles #1 and #2 Units Standard Alternate Min Max AutoStore/Power Up RecallSymbols Parameter Software-Controlled STORE/RECALL Cycle Hardware Store Pulse Width Soft Sequence CommandsHardware Store to Sram Disabled Hardware Store CycleA16-A0 Mode Power Mode SelectionAutoStore Operation Hardware Recall POWER-UPNvSRAM Operation Hardware Store HSB OperationNoise Considerations Low Average Active PowerSoftware Recall Data ProtectionRTC Operations Calibrating The Clock Watchdog TimerAlarm Power MonitorInterrupt Register InterruptsFlags Register Register BCD Format Data Function / Range RTC RegisterRegister Map Detail 0x1FFF6 Interrupt 0x1FFF5 Alarm Day0x1FFF4 Alarm Hours 0x1FFF7WDF Oscf CAL 0x1FFF2 Alarm Seconds0x1FFF1 Real Time Clock Centuries 10s Centuries 0x1FFF0 FlagsOrdering Codes Ordering Information51-85061 *C Document # 001-52039 Rev Package DiagramsDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions