Cypress STK17TA8 manual Features, Description, Logic Block Diagram

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STK17TA8

128k X 8 AutoStore™ nvSRAM with Real Time Clock

Features

nvSRAM Combined with Integrated Real Time Clock Functions (RTC, Watchdog Timer, Clock Alarm, Power Monitor)

Capacitor or Battery Backup for RTC

25, 45 ns Read Access and Read/Write Cycle Time

Unlimited Read/Write Endurance

Automatic nonvolatile STORE on Power Loss

Nonvolatile STORE Under Hardware or Software Control

Automatic RECALL to SRAM on Power Up

Unlimited RECALL Cycles

200K STORE Cycles

20-Year nonvolatile Data Retention

Single 3 V +20%, -10% Power Supply

Commercial and Industrial Temperatures

48-pin 300-mil SSOP Package (RoHS-Compliant)

Description

The Cypress STK17TA8 combines a 1 Mb nonvolatile static RAM (nvSRAM) with a full featured real time clock in a reliable, monolithic integrated circuit.

The 1 Mb nvSRAM is a fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell.

The SRAM provides the fast access and cycle times, ease of use and unlimited read and write endurance of a normal SRAM. Data transfers automatically to the nonvolatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control.

The real time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The Alarm function is programmable for one-time alarms or periodic minutes, hours, or days alarms. There is also a programmable watchdog timer for processor control.

Logic Block Diagram

 

 

Quantum Trap

VCC

VCAP

 

 

 

 

 

 

 

 

A5

 

1024 X 1024

POWER

VRTCbat

 

 

 

 

 

A6

DECODER

 

STORE

CONTROL

VRTCcap

 

A7

 

 

 

 

 

 

 

 

 

A8

STATIC RAM

 

STORE/

 

 

A9

RECALL

 

 

ARRAY

RECALL

 

 

A12

 

HSB

 

A13

ROW

1024 X 1024

 

CONTROL

 

A14

 

 

 

 

 

 

A15

 

 

 

 

SOFTWARE

 

A16

 

 

 

 

A15 – A0

 

 

 

 

 

DETECT

 

DQ0

BUFFERS

COLUMN I/O

 

 

 

 

 

DQ1

 

 

 

 

X1

DQ2

COLUMN DEC

 

 

RTC

 

DQ3

 

 

 

 

X2

DQ4

 

 

 

 

 

INT

INPUT

 

 

 

 

 

DQ5

A0 A1 A2 A3 A4 A10 A11

 

 

 

 

 

DQ6

 

 

 

MUX

 

A16 – A0

DQ7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

W

Cypress Semiconductor Corporation • 198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document #: 001-52039 Rev. **

 

Revised March 02, 2009

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Contents Logic Block Diagram FeaturesDescription Cypress Semiconductor Corporation 198 Champion CourtPin Descriptions PinoutsRF SSOP-48 Package Thermal Characteristics DC Electrical CharacteristicsSymbol Parameter Commercial Industrial Units Min Absolute Maximum RatingsSymbol Parameter Max Units Conditions Symbol Parameter Commercial Industrial Units Min MaxAC Test Conditions CapacitanceRTC DC Characteristics Sram Read Cycles #1 and #2 Symbols Parameter STK17TA8-25 STK17TA8-45 Units Alt Min MaxSram Write Cycles #1 and #2 Symbols Parameter AutoStore/Power Up RecallUnits Standard Alternate Min Max Software-Controlled STORE/RECALL Cycle Hardware Store to Sram Disabled Soft Sequence CommandsHardware Store Cycle Hardware Store Pulse WidthA16-A0 Mode Power Mode SelectionNvSRAM Operation Hardware Recall POWER-UPHardware Store HSB Operation AutoStore OperationSoftware Recall Low Average Active PowerData Protection Noise ConsiderationsRTC Operations Alarm Watchdog TimerPower Monitor Calibrating The ClockFlags Register InterruptsInterrupt Register Register BCD Format Data Function / Range RTC RegisterRegister Map Detail 0x1FFF4 Alarm Hours 0x1FFF5 Alarm Day0x1FFF7 0x1FFF6 Interrupt0x1FFF1 Real Time Clock Centuries 10s Centuries 0x1FFF2 Alarm Seconds0x1FFF0 Flags WDF Oscf CALOrdering Codes Ordering Information51-85061 *C Document # 001-52039 Rev Package DiagramsWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History