Cypress STK17TA8 manual Package Diagrams, 51-85061 *C Document # 001-52039 Rev

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STK17TA8

Package Diagrams

Figure 17. 48-Pin SSOP (51-85061)

51-85061 *C

Document #: 001-52039 Rev. **

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Contents Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtPinouts Pin DescriptionsSymbol Parameter Commercial Industrial Units Min DC Electrical CharacteristicsRF SSOP-48 Package Thermal Characteristics Absolute Maximum RatingsAC Test Conditions Symbol Parameter Commercial Industrial Units Min MaxSymbol Parameter Max Units Conditions CapacitanceRTC DC Characteristics Symbols Parameter STK17TA8-25 STK17TA8-45 Units Alt Min Max Sram Read Cycles #1 and #2Sram Write Cycles #1 and #2 Symbols Parameter AutoStore/Power Up RecallUnits Standard Alternate Min Max Software-Controlled STORE/RECALL Cycle Hardware Store Cycle Soft Sequence CommandsHardware Store to Sram Disabled Hardware Store Pulse WidthMode Selection A16-A0 Mode PowerHardware Store HSB Operation Hardware Recall POWER-UPNvSRAM Operation AutoStore OperationData Protection Low Average Active PowerSoftware Recall Noise ConsiderationsRTC Operations Power Monitor Watchdog TimerAlarm Calibrating The ClockFlags Register InterruptsInterrupt Register RTC Register Register BCD Format Data Function / RangeRegister Map Detail 0x1FFF7 0x1FFF5 Alarm Day0x1FFF4 Alarm Hours 0x1FFF6 Interrupt0x1FFF0 Flags 0x1FFF2 Alarm Seconds0x1FFF1 Real Time Clock Centuries 10s Centuries WDF Oscf CALOrdering Information Ordering CodesPackage Diagrams 51-85061 *C Document # 001-52039 RevWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History
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