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| CY7C1330AV25 |
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| PRELIMINARY |
| CY7C1332AV25 |
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Switching Characteristics[18, 19, 20, 21] |
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| 250 |
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Parameter |
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| Description |
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| Unit |
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| Min. |
| Max. | Min. |
| Max. |
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t |
| V | CC | (typical) to the First Access Read or Write[22] | 1 |
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| 1 |
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| ms |
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Power |
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Clock |
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tCYC |
| Clock Cycle Time | 4.0 |
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| 5.0 |
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| ns |
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FMAX |
| Maximum Operating Frequency |
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| 200 | MHz |
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tCH |
| Clock HIGH | 1.5 |
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| 1.5 |
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| ns |
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tCL |
| Clock LOW | 1.5 |
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| 1.5 |
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| ns |
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Output Times |
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tCO |
| Data Output Valid After CLK Rise |
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| 2.0 |
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| 2.25 | ns |
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tEOV |
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| LOW to Output Valid[17, 19, 21] |
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| 2.0 |
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| 2.25 | ns |
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OE |
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tDOH |
| Data Output Hold After CLK Rise | 0.5 |
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| 0.5 |
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tCHZ |
| Clock to |
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| 2.0 |
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| 2.25 | ns |
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t |
| Clock to | 0.5 |
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| 0.5 |
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CLZ |
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t |
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| HIGH to Output |
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| 2.0 |
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| 2.25 | ns |
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OE |
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EOHZ |
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tEOLZ |
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| LOW to Output | 0.5 |
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| 0.5 |
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OE |
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tAS |
| Address | 0.3 |
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| 0.3 |
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tDS |
| Data Input | 0.3 |
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| 0.3 |
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tWES |
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| x | 0.3 |
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| 0.3 |
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WE, | BWS |
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tCES |
| Chip Select | 0.3 |
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| 0.3 |
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Hold Times |
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tAH |
| Address Hold After CLK Rise | 0.6 |
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| 0.6 |
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tDH |
| Data Input Hold After CLK Rise | 0.6 |
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| 0.6 |
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tWEH |
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| x Hold After CLK Rise | 0.6 |
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| 0.6 |
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WE, | BW |
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tCEH |
| Chip Select Hold After CLK Rise | 0.6 |
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| 0.6 |
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Notes:
19.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from
20.At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
21.This parameter is sampled and not 100% tested.
22.This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a read or write operation can be initiated.
Document No: | Page 15 of 19 |
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