Cypress CY7C1330AV25 manual Selection Guide, Pin Configurations Ball BGA 14 x 22 x 2.4 mm, Unit

Page 2

CY7C1330AV25

PRELIMINARY

CY7C1332AV25

Selection Guide

CY7C1330AV25-250

CY7C1330AV25-200

Unit

CY7C1332AV25-250

CY7C1332AV25- 200

Maximum Access Time

2.0

2.25

ns

Maximum Operating Current

600

550

mA

Maximum CMOS Standby Current

280

260

mA

Pin Configurations

119-Ball BGA (14 x 22 x 2.4 mm)

CY7C1330AV25 (512K x 36)

1

2

3

4

5

6

7

A

VDDQ

A

A

NC

A

A

VDDQ

B

NC

A

A

NC

A

A

NC

C

NC

A

A

VDD

A

A

NC

D

DQc

DQc

VSS

ZQ

VSS

DQb

DQb

E

DQc

DQc

VSS

CE

VSS

DQb

DQb

F

VDDQ

DQc

VSS

OE

VSS

DQb

VDDQ

G

DQc

DQc

BWS

c

NC

BWS

b

DQb

DQb

H

DQc

DQc

VSS

NC

VSS

DQb

DQb

J

VDDQ

VDD

VREF

VDD

VREF

VDD

VDDQ

K

DQd

DQd

VSS

K

VSS

DQa

DQa

L

DQd

DQd

BWS

d

K

BWS

a

DQa

DQa

M

VDDQ

DQd

VSS

WE

VSS

DQa

VDDQ

N

DQd

DQd

VSS

A0

VSS

DQa

DQa

P

DQd

DQd

VSS

A1

VSS

DQa

DQa

R

NC

A

M1

VDD

M2

A

NC

T

NC

NC

A

A

A

NC

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

CY7C1332AV25 (1M x 18)

1

2

3

4

5

6

7

A

VDDQ

A

A

NC

A

A

VDDQ

B

NC

A

A

NC

A

A

NC

C

NC

A

A

VDD

A

A

NC

D

DQb

NC

VSS

ZQ

VSS

DQa

NC

E

NC

DQb

VSS

CE

VSS

NC

DQa

F

VDDQ

NC

VSS

OE

VSS

DQa

VDDQ

G

NC

DQb

BWS

b

NC

NC

NC

DQa

H

DQb

NC

VSS

NC

VSS

DQa

NC

J

VDDQ

VDD

VREF

VDD

VREF

VDD

VDDQ

K

NC

DQb

VSS

K

VSS

NC

DQa

L

DQb

NC

NC

K

BWS

a

DQa

NC

M

VDDQ

DQb

VSS

WE

VSS

NC

VDDQ

N

DQb

NC

VSS

A0

VSS

DQa

NC

P

NC

DQb

VSS

A1

VSS

NC

DQa

R

NC

A

M1

VDD

M2

A

NC

T

NC

A

A

NC

A

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Document No: 001-07844 Rev. *A

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Contents Logic Block Diagram FeaturesConfiguration Functional DescriptionSelection Guide Pin Configurations Ball BGA 14 x 22 x 2.4 mmMaximum Access Time Maximum Operating Current UnitByte Write Select Inputs, active LOW. Qualified with Pin DefinitionsName Type Description Serial clock to the Jtag circuit No connectsFunctional Overview Sleep ModeIntroduction Write Cycle Descriptions 1 ZZ Mode Electrical CharacteristicsCycle Description Truth , 2, 3, 4 Write Cycle Descriptions1Ieee 1149.1 Serial Boundary Scan Jtag Extest TAP Controller State Diagram6 EXIT2-IR UPDATE-DR UPDATE-IRParameter Description Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics Over the Operating Range7, 8 Set-up TimesParameter Description Min TAP Timing and Test Conditions11Identification Register Definitions Output TimesBoundary Scan Order 1 Mbit x Scan Register SizesInstruction Codes Boundary Scan Order 512K x Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance17Thermal Resistance17 Parameter Description Test Conditions Max UnitClock Switching Characteristics 18, 19, 20250 200 Parameter Description Unit Min Max = DON’T Care = Undefined Switching WaveformsREAD/WRITE/DESELECT Sequence OE Controlled23, 24, 25 READ/WRITE/DESELECT Sequence CE Controlled Originally DeselectedBall Pbga 14 x 22 x 2.4 mm Package DiagramOrdering Information Minor change Moved data sheet to web ECN No Issue Date Orig. Description of ChangeNew data sheet Document History