Cypress CY7C1330AV25 manual Ordering Information, Package Diagram, Ball Pbga 14 x 22 x 2.4 mm

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CY7C1330AV25

PRELIMINARYCY7C1332AV25

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

Ordering Code

Package

Package Type

Operating

(MHz)

Diagram

Range

 

 

 

 

 

250

CY7C1330AV25-250BGC

51-85115

119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm)

Commercial

 

CY7C1332AV25-250BGC

 

 

 

 

CY7C1330AV25-250BGXC

51-85115

119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

 

 

CY7C1332AV25-250BGXC

 

 

 

200

CY7C1330AV25-200BGC

51-85115

119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm)

 

 

CY7C1332AV25-200BGC

 

 

 

 

CY7C1330AV25-200BGXC

51-85115

119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

 

 

CY7C1332AV25-200BGXC

 

 

 

Package Diagram

119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)

51-85115-*B

All product and company names mentioned in this document are trademarks of their respective holders.

Document No: 001-07844 Rev. *A

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© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Contents Logic Block Diagram FeaturesConfiguration Functional DescriptionSelection Guide Pin Configurations Ball BGA 14 x 22 x 2.4 mmMaximum Access Time Maximum Operating Current UnitByte Write Select Inputs, active LOW. Qualified with Pin DefinitionsName Type Description Serial clock to the Jtag circuit No connectsSleep Mode IntroductionFunctional Overview Write Cycle Descriptions 1 ZZ Mode Electrical CharacteristicsCycle Description Truth , 2, 3, 4 Write Cycle Descriptions1Ieee 1149.1 Serial Boundary Scan Jtag Extest TAP Controller State Diagram6 EXIT2-IR UPDATE-DR UPDATE-IRParameter Description Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics Over the Operating Range7, 8 Set-up TimesParameter Description Min TAP Timing and Test Conditions11Identification Register Definitions Output TimesScan Register Sizes Instruction CodesBoundary Scan Order 1 Mbit x Boundary Scan Order 512K x Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance17Thermal Resistance17 Parameter Description Test Conditions Max UnitSwitching Characteristics 18, 19, 20 250 200 Parameter Description Unit Min MaxClock Switching Waveforms READ/WRITE/DESELECT Sequence OE Controlled23, 24, 25= DON’T Care = Undefined READ/WRITE/DESELECT Sequence CE Controlled Originally DeselectedPackage Diagram Ordering InformationBall Pbga 14 x 22 x 2.4 mm Minor change Moved data sheet to web ECN No Issue Date Orig. Description of ChangeNew data sheet Document History
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