Cypress CY7C1332AV25, CY7C1330AV25 manual Extest

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CY7C1330AV25

PRELIMINARYCY7C1332AV25

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction.

When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Document No: 001-07844 Rev. *A

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Contents Functional Description FeaturesConfiguration Logic Block DiagramUnit Pin Configurations Ball BGA 14 x 22 x 2.4 mmMaximum Access Time Maximum Operating Current Selection GuideSerial clock to the Jtag circuit No connects Pin DefinitionsName Type Description Byte Write Select Inputs, active LOW. Qualified withIntroduction Sleep ModeFunctional Overview Write Cycle Descriptions1 ZZ Mode Electrical CharacteristicsCycle Description Truth , 2, 3, 4 Write Cycle Descriptions 1Ieee 1149.1 Serial Boundary Scan Jtag Extest EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram6Set-up Times TAP Controller Block DiagramTAP Electrical Characteristics Over the Operating Range7, 8 Parameter Description Min Max UnitOutput Times TAP Timing and Test Conditions11Identification Register Definitions Parameter Description MinInstruction Codes Scan Register SizesBoundary Scan Order 1 Mbit x Boundary Scan Order 512K x Ambient Range Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeParameter Description Test Conditions Max Unit Capacitance17Thermal Resistance17 AC Test Loads and Waveforms250 200 Parameter Description Unit Min Max Switching Characteristics 18, 19, 20Clock READ/WRITE/DESELECT Sequence OE Controlled23, 24, 25 Switching Waveforms= DON’T Care = Undefined Originally Deselected READ/WRITE/DESELECT Sequence CE ControlledOrdering Information Package DiagramBall Pbga 14 x 22 x 2.4 mm Document History ECN No Issue Date Orig. Description of ChangeNew data sheet Minor change Moved data sheet to web
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