Cypress CY7C1330AV25 manual Capacitance17, Thermal Resistance17, AC Test Loads and Waveforms

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CY7C1330AV25

 

 

 

 

 

 

 

PRELIMINARY

CY7C1332AV25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Capacitance[17]

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

Description

 

Test Conditions

 

 

Max.

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

CIN

 

Input Capacitance

 

TA = 25°C, f = 1 MHz,

 

 

5

 

pF

 

 

 

 

 

 

VDD = 2.5V

 

 

 

 

 

 

CCLK

 

Clock Input Capacitance

 

 

 

6

 

pF

 

 

 

 

 

 

 

 

 

VDDQ = 1.5V

 

 

 

 

 

 

CI/O

 

Input/Output Capacitance

 

 

 

7

 

pF

 

 

 

 

 

 

 

 

Thermal Resistance[17]

 

 

 

 

 

 

 

 

 

 

Parameter

Description

 

 

Test Conditions

 

 

BGA Typ.

 

Unit

 

 

 

 

 

 

 

 

 

 

ΘJA

Thermal Resistance

 

Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed

 

19.7

 

°C/W

 

 

(Junction to Ambient)

 

circuit board

 

 

 

 

 

 

 

 

ΘJC

Thermal Resistance

 

 

 

 

 

6.0

 

°C/W

 

 

(Junction to Case)

 

 

 

 

 

 

 

 

 

 

AC Test Loads and Waveforms

VREF

 

 

 

 

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

Z0 = 50

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

Under

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

 

 

 

 

 

 

 

 

 

 

ZQ

RQ =

250

(a)

RL = 50

VREF = 0.75V

 

 

 

 

 

 

VREF = 0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF

 

 

 

 

0.75V

 

 

 

R = 50

[18]

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

ALL INPUT PULSES

 

 

 

 

 

 

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

 

5 pF 0.25V

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Under

ZQ

 

 

 

 

 

 

 

 

 

 

Slew Rate = 2 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

RQ =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

250

(b)

Notes:

17.Tested initially and after any design or process change that may affect these parameters.

18.Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.

Document No: 001-07844 Rev. *A

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Contents Logic Block Diagram FeaturesConfiguration Functional DescriptionSelection Guide Pin Configurations Ball BGA 14 x 22 x 2.4 mmMaximum Access Time Maximum Operating Current UnitByte Write Select Inputs, active LOW. Qualified with Pin DefinitionsName Type Description Serial clock to the Jtag circuit No connectsFunctional Overview Sleep ModeIntroduction Write Cycle Descriptions 1 ZZ Mode Electrical CharacteristicsCycle Description Truth , 2, 3, 4 Write Cycle Descriptions1Ieee 1149.1 Serial Boundary Scan Jtag Extest TAP Controller State Diagram6 EXIT2-IR UPDATE-DR UPDATE-IRParameter Description Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics Over the Operating Range7, 8 Set-up TimesParameter Description Min TAP Timing and Test Conditions11Identification Register Definitions Output TimesBoundary Scan Order 1 Mbit x Scan Register SizesInstruction Codes Boundary Scan Order 512K x Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance17Thermal Resistance17 Parameter Description Test Conditions Max UnitClock Switching Characteristics 18, 19, 20250 200 Parameter Description Unit Min Max = DON’T Care = Undefined Switching WaveformsREAD/WRITE/DESELECT Sequence OE Controlled23, 24, 25 READ/WRITE/DESELECT Sequence CE Controlled Originally DeselectedBall Pbga 14 x 22 x 2.4 mm Package DiagramOrdering Information Minor change Moved data sheet to web ECN No Issue Date Orig. Description of ChangeNew data sheet Document History