Cypress CY7C1306BV25, CY7C1303BV25 TAP Controller State Diagram9, EXIT2-IR UPDATE-DR UPDATE-IR

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CY7C1303BV25

CY7C1306BV25

TAP Controller State Diagram[9]

TEST-LOGIC RESET

TEST-LOGIC/ IDLE

Note:

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document #: 38-05627 Rev. *A

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Contents Functional Description FeaturesConfigurations CY7C1303BV25 1M x CY7C1306BV25 512K xSelection Guide Logic Block Diagram CY7C1303BV25Logic Block Diagram CY7C1306BV25 CY7C1303BV25-167 UnitPin Configuration Ball Fbga 13 x 15 x 1.4 mm Pinout CY7C1306BV25 512K xPin Definitions Introduction Depth Expansion Application Example1Concurrent Transactions Programmable ImpedanceWrite Descriptions CY7C1306BV25 2 Write Descriptions CY7C1303BV25 2Comments Ieee 1149.1 Serial Boundary Scan Jtag Sample Z TAP Controller State Diagram9 EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram TAP AC Switching Characteristics Over the Operating Range11Identification Register Definitions TAP Timing and Test Conditions12Parameter Description Min Max Unit Output Times Register Name Bit Size Scan Register SizesInstruction Codes Instruction Code DescriptionBoundary Scan Order Bit # Bump IDOperating Range Maximum RatingsThermal Resistance AC Test Loads and Waveforms Switching Characteristics Over the Operating RangeCapacitance Parameter Description Test ConditionsSwitching Waveforms25, 26 Write Read NOPCY7C1306BV25-167BZC CY7C1303BV25-167BZXC Package DiagramOrdering Information CY7C1306BV25-167BZI CY7C1303BV25-167BZXISYT Issue Date Orig. Description of ChangeDocument History NXR