Cypress CY7C1303BV25 manual Document History, Issue Date Orig. Description of Change, Syt, Nxr

Page 19

CY7C1303BV25

CY7C1306BV25

Document History Page

Document Title: CY7C1303BV25/CY7C1306BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture

Document Number: 38-05627

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

253010

See ECN

SYT

New Data Sheet

 

 

 

 

 

*A

436864

See ECN

NXR

Converted from Preliminary to Final.

 

 

 

 

Removed 133 MHz & 100 MHz from product offering.

 

 

 

 

Included the Industrial Operating Range.

 

 

 

 

Changed C/C Description in the Features Section & Pin Description Table.

 

 

 

 

Changed tTCYC from 100 ns to 50 ns, changed tTF from 10 MHz to 20 MHz

 

 

 

 

and changed tTH and tTL from 40 ns to 20 ns in TAP AC Switching

 

 

 

 

Characteristics table

 

 

 

 

Modified the ZQ pin definition as follows:

 

 

 

 

Alternately, this pin can be connected directly to VDDQ, which enables the

 

 

 

 

minimum impedance mode

 

 

 

 

Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD.

 

 

 

 

Modified the Description of IX from Input Load current to Input Leakage

 

 

 

 

Current on page # 15.

 

 

 

 

Modified test condition in note# 13 from VDDQ < VDD to VDDQ ≤ VDD

 

 

 

 

Updated the Ordering Information table and replaced the Package Name

 

 

 

 

Column with Package Diagram.

Document #: 38-05627 Rev. *A

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Contents CY7C1303BV25 1M x CY7C1306BV25 512K x FeaturesConfigurations Functional DescriptionCY7C1303BV25-167 Unit Logic Block Diagram CY7C1303BV25Logic Block Diagram CY7C1306BV25 Selection GuideCY7C1306BV25 512K x Pin Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutPin Definitions Introduction Programmable Impedance Application Example1Concurrent Transactions Depth ExpansionWrite Descriptions CY7C1306BV25 2 Write Descriptions CY7C1303BV25 2Comments Ieee 1149.1 Serial Boundary Scan Jtag Sample Z EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram9TAP AC Switching Characteristics Over the Operating Range11 TAP Controller Block DiagramIdentification Register Definitions TAP Timing and Test Conditions12Parameter Description Min Max Unit Output Times Instruction Code Description Scan Register SizesInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderOperating Range Maximum RatingsThermal Resistance Parameter Description Test Conditions Switching Characteristics Over the Operating RangeCapacitance AC Test Loads and WaveformsWrite Read NOP Switching Waveforms25, 26CY7C1306BV25-167BZI CY7C1303BV25-167BZXI Package DiagramOrdering Information CY7C1306BV25-167BZC CY7C1303BV25-167BZXCNXR Issue Date Orig. Description of ChangeDocument History SYT
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