Cypress CY7C1303BV25, CY7C1306BV25 manual TAP Controller Block Diagram

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CY7C1303BV25

CY7C1306BV25

TAP Controller Block Diagram

TDI

 

 

 

 

 

 

0

 

 

 

 

 

 

Bypass Register

 

 

Selection

 

 

 

2

1

0

Selection

TDO

Circuitry

Instruction Register

 

 

Circuitry

 

 

 

 

 

 

31

30 29 .

.

2

1

0

 

 

 

Identification Register

 

 

 

106

. .

.

.

2

1

0

 

 

 

Boundary Scan Register

 

 

 

TCK TMS

TAP Controller

TAP Electrical Characteristics Over the Operating Range [10, 14, 17]

Parameter

Description

Test Conditions

Min.

Max.

Unit

VOH1

Output HIGH Voltage

IOH = 2.0 mA

1.7

 

V

VOH2

Output HIGH Voltage

IOH = 100 A

2.1

 

V

VOL1

Output LOW Voltage

IOL = 2.0 mA

 

0.7

V

VOL2

Output LOW Voltage

IOL = 100 A

 

0.2

V

VIH

Input HIGH Voltage

 

1.7

VDD + 0.3

V

VIL

Input LOW Voltage

 

–0.3

0.7

V

IX

Input and Output Load Current

GND VI VDDQ

5

5

A

TAP AC Switching Characteristics Over the Operating Range[11, 12]

Parameter

Description

Min.

Max.

Unit

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH

20

 

ns

tTL

TCK Clock LOW

20

 

ns

Set-up Times

 

 

 

 

 

 

 

 

 

tTMSS

TMS Set-up to TCK Clock Rise

10

 

ns

tTDIS

TDI Set-up to TCK clock Rise

10

 

ns

tCS

Capture Set-up to TCK Rise

10

 

ns

Hold Times

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

10

 

ns

tTDIH

TDI Hold after Clock Rise

10

 

ns

tCH

Capture Hold after Clock Rise

10

 

ns

Notes:

10.These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

11.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

12.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

Document #: 38-05627 Rev. *A

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Contents CY7C1303BV25 1M x CY7C1306BV25 512K x FeaturesConfigurations Functional DescriptionCY7C1303BV25-167 Unit Logic Block Diagram CY7C1303BV25Logic Block Diagram CY7C1306BV25 Selection GuideCY7C1306BV25 512K x Pin Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutPin Definitions Introduction Programmable Impedance Application Example1Concurrent Transactions Depth ExpansionComments Write Descriptions CY7C1303BV25 2Write Descriptions CY7C1306BV25 2 Ieee 1149.1 Serial Boundary Scan Jtag Sample Z EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram9TAP AC Switching Characteristics Over the Operating Range11 TAP Controller Block DiagramParameter Description Min Max Unit Output Times TAP Timing and Test Conditions12Identification Register Definitions Instruction Code Description Scan Register SizesInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderThermal Resistance Maximum RatingsOperating Range Parameter Description Test Conditions Switching Characteristics Over the Operating RangeCapacitance AC Test Loads and WaveformsWrite Read NOP Switching Waveforms25, 26CY7C1306BV25-167BZI CY7C1303BV25-167BZXI Package DiagramOrdering Information CY7C1306BV25-167BZC CY7C1303BV25-167BZXCNXR Issue Date Orig. Description of ChangeDocument History SYT