Cypress CY7C1306BV25 manual TAP Timing and Test Conditions12, Identification Register Definitions

Page 12

CY7C1303BV25

CY7C1306BV25

TAP AC Switching Characteristics Over the Operating Range[11, 12] (continued)

Parameter

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

Min.

Max.

Unit

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tTDOV

 

TCK Clock LOW to TDO Valid

 

 

 

 

 

 

20

ns

tTDOX

 

TCK Clock LOW to TDO Invalid

 

 

 

 

 

0

 

ns

TAP Timing and Test Conditions[12]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50

 

 

 

ALL INPUT PULSES

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.5V

 

 

 

 

 

 

Z0 = 50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CL = 20 pF

0V

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)GND

tTH

tTL

Test Clock

TCK

Test Mode Select

TMS

Test Data-In

TDI

tTCYC tTMSS

tTMSH

tTDIS

tTDIH

Test Data-Out

TDO

tTDOX

tTDOV

Identification Register Definitions

 

Value

 

Instruction Field

CY7C1303BV25

CY7C1306BV25

Description

 

 

 

 

Revision Number (31:29)

000

000

Version number.

 

 

 

 

Cypress Device ID (28:12)

01011010010010101

01011010010100101

Defines the type of SRAM.

 

 

 

 

Cypress JEDEC ID (11:1)

00000110100

00000110100

Allows unique identification of SRAM vendor.

 

 

 

 

ID Register Presence (0)

1

1

Indicate the presence of an ID register.

 

 

 

 

Document #: 38-05627 Rev. *A

Page 12 of 19

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Contents Features ConfigurationsFunctional Description CY7C1303BV25 1M x CY7C1306BV25 512K xLogic Block Diagram CY7C1303BV25 Logic Block Diagram CY7C1306BV25Selection Guide CY7C1303BV25-167 UnitPin Configuration Ball Fbga 13 x 15 x 1.4 mm Pinout CY7C1306BV25 512K xPin Definitions Introduction Application Example1 Concurrent TransactionsDepth Expansion Programmable ImpedanceWrite Descriptions CY7C1303BV25 2 Write Descriptions CY7C1306BV25 2Comments Ieee 1149.1 Serial Boundary Scan Jtag Sample Z TAP Controller State Diagram9 EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram TAP AC Switching Characteristics Over the Operating Range11TAP Timing and Test Conditions12 Identification Register DefinitionsParameter Description Min Max Unit Output Times Scan Register Sizes Instruction CodesRegister Name Bit Size Instruction Code DescriptionBoundary Scan Order Bit # Bump IDMaximum Ratings Operating RangeThermal Resistance Switching Characteristics Over the Operating Range CapacitanceAC Test Loads and Waveforms Parameter Description Test ConditionsSwitching Waveforms25, 26 Write Read NOPPackage Diagram Ordering InformationCY7C1306BV25-167BZC CY7C1303BV25-167BZXC CY7C1306BV25-167BZI CY7C1303BV25-167BZXIIssue Date Orig. Description of Change Document HistorySYT NXR