Cypress CY7C1303BV25, CY7C1306BV25 manual Sample Z

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CY7C1303BV25

CY7C1306BV25

is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state.

EXTEST Output Bus Tri-state

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #47. When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Document #: 38-05627 Rev. *A

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Contents Configurations FeaturesFunctional Description CY7C1303BV25 1M x CY7C1306BV25 512K xLogic Block Diagram CY7C1306BV25 Logic Block Diagram CY7C1303BV25Selection Guide CY7C1303BV25-167 UnitCY7C1306BV25 512K x Pin Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutPin Definitions Introduction Concurrent Transactions Application Example1Depth Expansion Programmable ImpedanceWrite Descriptions CY7C1303BV25 2 Write Descriptions CY7C1306BV25 2Comments Ieee 1149.1 Serial Boundary Scan Jtag Sample Z EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram9TAP AC Switching Characteristics Over the Operating Range11 TAP Controller Block DiagramTAP Timing and Test Conditions12 Identification Register DefinitionsParameter Description Min Max Unit Output Times Instruction Codes Scan Register SizesRegister Name Bit Size Instruction Code DescriptionBit # Bump ID Boundary Scan OrderMaximum Ratings Operating RangeThermal Resistance Capacitance Switching Characteristics Over the Operating RangeAC Test Loads and Waveforms Parameter Description Test ConditionsWrite Read NOP Switching Waveforms25, 26Ordering Information Package DiagramCY7C1306BV25-167BZC CY7C1303BV25-167BZXC CY7C1306BV25-167BZI CY7C1303BV25-167BZXIDocument History Issue Date Orig. Description of ChangeSYT NXR
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