Cypress CY7C1346H manual Document History, Issue Date Orig. Description of Change, Pci, Rxu, Nxr

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CY7C1346H

Document History Page

Document Title: CY7C1346H 2-Mbit (64K x 36) Pipelined Sync SRAM

Document Number: 38-05672

REV.	ECN NO.	Issue Date	Orig. of	Description of Change
REV.	ECN NO.	Issue Date	Change	Description of Change

**	347357	See ECN	PCI	New Data sheet

*A	420879	See ECN	RXU	Converted from Preliminary to Final.
				Changed address of Cypress Semiconductor Corporation on Page# 1 from
				“3901 North First Street” to “198 Champion Court”
				Removed 133MHz Speed bin.
				Changed three-state to tri-state.
				Modified test condition from VIH < VDD to VIH < VDD
				Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
				Electrical Characteristics Table.
				Replaced Package Name column with Package Diagram in the Ordering
				Information table.
				Replaced Package Diagram of 51-85050 from A to B
*B	459347	See ECN	NXR	Included 2.5V I/O option
				Updated the Ordering Information table.

Document #: 38-05672 Rev. *B

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Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation Pin Configuration Selection GuideCY7C1346H 166 MHz UnitPower supply inputs to the core of the device Pin DefinitionsName Description Byte Write Select Inputs, active LOW . Qualified withFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Burst SequencesNext Cycle Add. Used Adsp Adsc ADV Write CLKTruth Table for Read/Write2 FunctionOperating Range Maximum RatingsAmbient Range Thermal Resistance10 Capacitance10AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 11 Switching Waveforms Read Cycle Timing17Write Cycle Timing17 ADVRead/Write Cycle Timing17, 19 CLZZZ Mode Timing 21 DON’T CareOrdering Information Package DiagramsPin Tqfp 14 x 20 x 1.4 mm Issue Date Orig. Description of Change Document HistoryPCI RXU