Cypress CY7C1346H manual Burst Sequences, Interleaved Burst Address Table Mode = Floating or VDD

CY7C1346H

Burst Sequences

The CY7C1346H provides a two-bit wraparound counter, fed by A1, A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specif- ically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input.

Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table (MODE = Floating or VDD)

First	Second	Third	Fourth
Address	Address	Address	Address
A1, A0	A1, A0	A1, A0	A1, A0
00	01	10	11
01	00	11	10
10	11	00	01
11	10	01	00

Linear Burst Address Table (MODE = GND)

First	Second	Third	Fourth
Address	Address	Address	Address
A1, A0	A1, A0	A1, A0	A1, A0
00	01	10	11
01	10	11	00
10	11	00	01
11	00	01	10

ZZ Mode Electrical Characteristics

Parameter	Description	Test Conditions	Min.	Max.	Unit
IDDZZ	Sleep mode standby current	ZZ > VDD – 0.2V		40	mA
tZZS	Device operation to ZZ	ZZ > VDD – 0.2V		2tCYC	ns
tZZREC	ZZ recovery time	ZZ < 0.2V	2tCYC		ns
tZZI	ZZ Active to sleep current	This parameter is sampled		2tCYC	ns
tRZZI	ZZ Inactive to exit sleep current	This parameter is sampled	0		ns

Document #: 38-05672 Rev. *B Page 5 of 16

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