Cypress CY7C1346H manual Write Cycle Timing17, Adv

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CY7C1346H

Switching Waveforms (continued)

Write Cycle Timing[17, 18]

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A :D]

GW

CE

ADV

OE

Data In (D)

		tCYC
	tCH	tCL
tADS	tADH
		tADS	tADH	ADSC extends burst
		tADS	tADH	tADS	tADH
				tADS	tADH
tAS	tAH
	A1			A2	A3
	Byte write signals are
	ignored for first cycle when				tWES tWEH
	ADSP initiates burst				tWES tWEH

tWES tWEH

tCES	tCEH
								tADVS tADVH
				ADV suspends burst
	tDS tDH
High-Z	D(A1)	D(A2)	D(A2 + 1)	D(A2 + 1)	D(A2 + 2)	D(A2 + 3)	D(A3)	D(A3 + 1)	D(A3 + 2)
	t
	OEHZ

Data Out (Q)

BURST READ	Single WRITE	BURST WRITE
	DON’T CARE	UNDEFINED

Note:

18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Extended BURST WRITE

Document #: 38-05672 Rev. *B

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Contents Features Logic Block DiagramCypress Semiconductor Corporation Pin Configuration Selection GuideCY7C1346H 166 MHz UnitPower supply inputs to the core of the device Pin DefinitionsName Description Byte Write Select Inputs, active LOW . Qualified withFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Burst SequencesNext Cycle Add. Used Adsp Adsc ADV Write CLKTruth Table for Read/Write2 FunctionMaximum Ratings Operating RangeAmbient Range Capacitance10 Thermal Resistance10AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 11 Switching Waveforms Read Cycle Timing17Write Cycle Timing17 ADVRead/Write Cycle Timing17, 19 CLZZZ Mode Timing 21 DON’T CarePackage Diagrams Ordering InformationPin Tqfp 14 x 20 x 1.4 mm Issue Date Orig. Description of Change Document HistoryPCI RXU