Cypress CY8C23433, CY8C23533 manual Features, Logic Block Diagram

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CY8C23433, CY8C23533

PSoC® Programmable System-on-Chip™

Features

■Powerful Harvard Architecture Processor

❐M8C Processor Speeds to 24 MHz

❐8x8 Multiply, 32-Bit Accumulate

❐Low Power at High Speed

❐3.0 to 5.25V Operating Voltage

❐Industrial Temperature Range: -40°C to +85°C

■Advanced Peripherals (PSoC Blocks)

❐4 Rail-to-Rail analog PSoC Blocks Provide:

•Up to 14-Bit ADCs

•Up to 8-Bit DACs

•Programmable Gain Amplifiers

•Programmable Filters and Comparators

❐4 Digital PSoC Blocks Provide:

•8 to 32-Bit Timers, Counters, and PWMs

•CRC and PRS Modules

•Full-Duplex UART

•Multiple SPI™ Masters or Slaves

•Connectable to All GPIO Pins

❐Complex Peripherals by Combining Blocks

❐High-Speed 8-Bit SAR ADC Optimized for Motor Control

■Precision, Programmable Clocking

❐Internal ±2.5% 24/48 MHz Oscillator

❐High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL

❐Optional External Oscillator, up to 24 MHz

❐Internal Oscillator for Watchdog and Sleep

■Flexible On-Chip Memory

❐8K Bytes Flash Program Storage 50,000 Erase/Write Cycles

❐256 Bytes SRAM Data Storage

❐In-System Serial Programming (ISSP)

❐Partial Flash Updates

❐Flexible Protection Modes

❐EEPROM Emulation in Flash

■Programmable Pin Configurations

❐25 mA Sink on all GPIO

❐Pull up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO

❐Up to Ten Analog Inputs on GPIO

❐Two 30 mA Analog Outputs on GPIO

❐Configurable Interrupt on All GPIO

■Additional System Resources

❐I2C™ Slave, Master, and Multi-Master to 400 kHz

❐Watchdog and Sleep Timers

❐User-Configurable Low Voltage Detection

❐Integrated Supervisory Circuit

❐On-chip Precision Voltage Reference

■Complete Development Tools

❐Free Development Software (PSoC Designer™)

❐Full-Featured In-Circuit Emulator and Programmer

❐Full Speed Emulation

❐Complex Breakpoint Structure

❐128K Bytes Trace Memory

Logic Block Diagram

 

 

 

 

 

Port 3

Port 2 Port 1

Port 0

Analog

 

 

Drivers

PSoC CORE

 

 

 

 

System Bus

 

 

 

 

 

Global Digital Interconnect

 

Global Analog Interconnect

 

 

 

 

SRAM

SROM

Flash 8K

 

 

256 Bytes

 

 

 

 

 

 

 

Interrupt

CPUCore(M8C)

Sleep and

 

 

 

Watchdog

Controller

 

 

 

 

 

 

 

 

 

 

Multiple ClockSources

 

 

 

(Includes IMO, ILO, PLL, and ECO)

 

DIGITAL SYSTEM

ANALOG SYSTEM

 

Digital

 

Analog

Analog

 

 

Ref

 

Block

 

Block Array

 

 

 

Array

 

2 Columns

 

 

 

 

 

 

 

 

1 Row

 

4 Blocks

Analog

 

4 Blocks

 

 

 

 

 

SAR8 ADC

Input

 

 

 

 

 

 

 

 

Muxing

Digital

Multiply

Decimator

 

POR and LVD

Internal

I2C

Voltage

Clocks

Accum.

System Resets

 

 

Ref.

 

 

 

 

 

 

 

SYSTEM RESOURCES

 

 

Cypress Semiconductor Corporation • 198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document Number: 001-44369 Rev. *B

 

Revised December 05, 2008

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Contents Logic Block Diagram FeaturesDigital System PSoC Functional OverviewPSoC Core Analog System Analog System Block DiagramGetting Started PSoC Device CharacteristicsAdditional System Resources Development Kits Technical Training ModulesPSoC Designer Software Subsystems Development ToolsDevice Editor Design BrowserHardware Tools Designing with User ModulesApplication Editor DebuggerUnits of Measure Document ConventionsNumeric Naming Acronyms UsedPin Part Pinout PinoutsSCL, ISSP-SCLK SDA, ISSP-SDATAPin Pin Definitions 28-Pin Ssop Number Name DescriptionI2C SCL I2C SDARegister Conventions Register ReferenceRegister Mapping Tables Abbreviations UsedRegister Map Bank 0 Table User Space Name Addr 1,Hex Access Register Map Bank 1 Table Configuration SpaceACB01CR0 RDI0RO0 ACB01CR1 RDI0RO1 Units of Measure Electrical SpecificationsAbsolute Maximum Ratings Symbol Description Min Typ Units Operating TemperatureOperating Temperature Symbol Description Min Typ Max Units Absolute Maximum RatingsDC Chip-Level Specifications DC Electrical CharacteristicsDC General Purpose IO Specifications Psrroa DC Operational Amplifier SpecificationsLow power comparator LPC reference voltage Vdd Range DC Low Power Comparator SpecificationsLPC supply current LPC voltage offset Document Number 001-44369 Rev. *BPsrrob DC Analog Output Buffer SpecificationsDC Analog Reference Specifications DC POR and LVD Specifications DC Analog PSoC Block SpecificationsDC Programming Specifications INL SAR8 ADC DC SpecificationsDNL AC Chip-Level Specifications AC Electrical CharacteristicsPLL EnableGain 32K SelectAC Operational Amplifier Specifications AC General Purpose IO SpecificationsBwoa CY8C23433, CY8C23533 Typical Agnd Noise with P24 Bypass AC Digital Block Specifications AC Low Power Comparator SpecificationsLarge Signal Bandwidth, 1Vpp, 3 dB BW, 100 pF Load AC Analog Output Buffer SpecificationsKHz Power = Low Power = High BwobAC Programming Specifications AC External Clock SpecificationsSAR8 ADC AC Specifications AC I2C Specifications Pin 5x5 mm QFN Packaging InformationSolder Reflow Peak Temperature Capacitance on Crystal PinsTypical Package Capacitance on Crystal Pins Thermal ImpedancesOrdering Information Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History Orig. Submission Description of Change Date