CY8C23433, CY8C23533
PSoC® Programmable System-on-Chip™
Features
■Powerful Harvard Architecture Processor
❐M8C Processor Speeds to 24 MHz
❐8x8 Multiply,
❐Low Power at High Speed
❐3.0 to 5.25V Operating Voltage
❐Industrial Temperature Range:
■Advanced Peripherals (PSoC Blocks)
❐4
•Up to
•Up to
•Programmable Gain Amplifiers
•Programmable Filters and Comparators
❐4 Digital PSoC Blocks Provide:
•8 to
•CRC and PRS Modules
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•Multiple SPI™ Masters or Slaves
•Connectable to All GPIO Pins
❐Complex Peripherals by Combining Blocks
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■Precision, Programmable Clocking
❐Internal ±2.5% 24/48 MHz Oscillator
❐High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐Optional External Oscillator, up to 24 MHz
❐Internal Oscillator for Watchdog and Sleep
■Flexible On-Chip Memory
❐8K Bytes Flash Program Storage 50,000 Erase/Write Cycles
❐256 Bytes SRAM Data Storage
❐
❐Partial Flash Updates
❐Flexible Protection Modes
❐EEPROM Emulation in Flash
■Programmable Pin Configurations
❐25 mA Sink on all GPIO
❐Pull up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO
❐Up to Ten Analog Inputs on GPIO
❐Two 30 mA Analog Outputs on GPIO
❐Configurable Interrupt on All GPIO
■Additional System Resources
❐I2C™ Slave, Master, and
❐Watchdog and Sleep Timers
❐
❐Integrated Supervisory Circuit
❐
■Complete Development Tools
❐Free Development Software (PSoC Designer™)
❐
❐Full Speed Emulation
❐Complex Breakpoint Structure
❐128K Bytes Trace Memory
Logic Block Diagram |
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| Port 3 | Port 2 Port 1 | Port 0 | Analog | ||
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| Drivers | |||||
PSoC CORE |
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System Bus |
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Global Digital Interconnect |
| Global Analog Interconnect | |||||
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SRAM | SROM | Flash 8K |
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256 Bytes |
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Interrupt | CPUCore(M8C) | Sleep and | |||||
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| Watchdog | ||||
Controller |
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| Multiple ClockSources |
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| (Includes IMO, ILO, PLL, and ECO) |
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DIGITAL SYSTEM | ANALOG SYSTEM | ||||||
| Digital |
| Analog | Analog | |||
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| Block |
| Block Array |
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| Array |
| 2 Columns |
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| 1 Row |
| 4 Blocks | Analog | |||
| 4 Blocks |
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| SAR8 ADC | Input | ||||
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| Muxing | ||
Digital | Multiply | Decimator |
| POR and LVD | Internal | ||
I2C | Voltage | ||||||
Clocks | Accum. | System Resets | |||||
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| Ref. | |||||
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| SYSTEM RESOURCES |
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Cypress Semiconductor Corporation • 198 Champion Court | • | San Jose, CA | • | |
Document Number: |
| Revised December 05, 2008 |
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