Cypress CY8C23533 manual Designing with User Modules, Hardware Tools, Application Editor, Debugger

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CY8C23433, CY8C23533

Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and can operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.

Designing with User Modules

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware and the software. This substantially lowers the risk of having to select a different part to meet the final design requirements.

To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called “User Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other uncommon peripherals such as DTMF Generators and Bi-Quad analog filter sections.

Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits

of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides high level functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that you can adapt as needed.

The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module.

The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions.

Figure 4. User Module/Source Code Development Flows

 

 

 

 

Device Editor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

User

 

 

Placement

 

 

 

Source

 

 

 

 

 

 

 

 

and

 

 

 

 

 

 

 

 

 

Module

 

 

 

 

 

Code

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Selection

 

 

 

 

 

Generator

 

 

 

 

 

 

 

 

-ization

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Application Editor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Project

 

 

Source

 

 

 

Build

 

 

 

 

 

 

 

 

Code

 

 

 

 

 

 

 

 

 

Manager

 

 

 

 

 

Manager

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Editor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Interface

 

 

Storage

 

 

 

Event &

 

 

 

 

 

 

 

 

 

 

Breakpoint

 

 

 

 

 

 

to ICE

 

 

Inspector

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Manager

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document Number: 001-44369 Rev. *B

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Contents Features Logic Block DiagramPSoC Functional Overview Digital SystemPSoC Core Analog System Block Diagram Analog SystemAdditional System Resources PSoC Device CharacteristicsGetting Started Development Kits Technical Training ModulesDevice Editor Development ToolsPSoC Designer Software Subsystems Design BrowserApplication Editor Designing with User ModulesHardware Tools DebuggerNumeric Naming Document ConventionsUnits of Measure Acronyms UsedSCL, ISSP-SCLK PinoutsPin Part Pinout SDA, ISSP-SDATAI2C SCL Pin Definitions 28-Pin Ssop Number Name DescriptionPin I2C SDARegister Mapping Tables Register ReferenceRegister Conventions Abbreviations UsedRegister Map Bank 0 Table User Space Register Map Bank 1 Table Configuration Space Name Addr 1,Hex AccessACB01CR0 RDI0RO0 ACB01CR1 RDI0RO1 Electrical Specifications Units of MeasureOperating Temperature Symbol Description Min Typ Max Units Operating TemperatureAbsolute Maximum Ratings Symbol Description Min Typ Units Absolute Maximum RatingsDC Electrical Characteristics DC Chip-Level SpecificationsDC General Purpose IO Specifications DC Operational Amplifier Specifications PsrroaLPC supply current DC Low Power Comparator SpecificationsLow power comparator LPC reference voltage Vdd Range LPC voltage offset Document Number 001-44369 Rev. *BDC Analog Output Buffer Specifications PsrrobDC Analog Reference Specifications DC Analog PSoC Block Specifications DC POR and LVD SpecificationsDC Programming Specifications SAR8 ADC DC Specifications INLDNL AC Electrical Characteristics AC Chip-Level SpecificationsGain EnablePLL 32K SelectAC General Purpose IO Specifications AC Operational Amplifier SpecificationsBwoa CY8C23433, CY8C23533 Typical Agnd Noise with P24 Bypass AC Low Power Comparator Specifications AC Digital Block SpecificationsKHz Power = Low Power = High AC Analog Output Buffer SpecificationsLarge Signal Bandwidth, 1Vpp, 3 dB BW, 100 pF Load BwobAC External Clock Specifications AC Programming SpecificationsSAR8 ADC AC Specifications AC I2C Specifications Packaging Information Pin 5x5 mm QFNTypical Package Capacitance on Crystal Pins Capacitance on Crystal PinsSolder Reflow Peak Temperature Thermal ImpedancesOrdering Information Document History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Orig. Submission Description of Change Date
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