CY8C23433, CY8C23533
Figure 9. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
FPLL
PLL
Gain 0
24 MHz
Figure 10. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW |
|
| 24 MHz |
|
| ||
| |||
|
|
FPLL
PLL
Gain 1
Figure 11. External Crystal Oscillator Startup Timing Diagram
32K
Select
F32K2
32 kHz
TOS
Figure 12. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F32K2
Document Number: | Page 26 of 37 |
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