Cypress CY7C025AV, CY7C024AV, CY7C026AV, CY7C024BV Write Cycle No R/W Controlled Timing 34, 35, 36

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Switching Waveforms (continued)

	Figure 8. Write Cycle No. 1: R/W Controlled Timing[34, 35, 36, 37]
		tWC
ADDRESS
			tHZOE[40]
OE
CE [38, 39]		tAW
	tSA	tPWE[37]	tHA
R/W
		tHZWE[40]	tLZWE
DATAOUT	NOTE 41		NOTE 41
		tSD	tHD
DATA IN

Figure 9. Write Cycle No. 2: CE Controlled Timing[34, 35, 36, 42]

ADDRESS

tWC

tAW

CE

[38, 39]

R/W

tSA	tSCE		tHA
		tSD		tHD

DATA IN

Notes

34.R/W or CE must be HIGH during all address transitions.

35.A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.

36.tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.

37.If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to enable the IO drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE.

38.To access RAM, CE = VIL, SEM = VIH.

39.To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH.

40.Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 percent tested.

41.During this period, the IO pins are in the output state, and input signals must not be applied.

42.If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.

Document #: 38-06052 Rev. *J Page 12 of 19

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