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| CY7C024AV/024BV/025AV/026AV | ||||||
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| CY7C0241AV/0251AV/036AV | ||||||
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Switching Characteristics |
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Over the Operating Range (continued)[20] |
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| CY7C024AV/024BV/025AV/026AV |
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Parameter |
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| Description |
| CY7C0241AV/0251AV/036AV |
| Unit | |||||||||||
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| Min |
| Max | Min |
| Max |
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tPWE |
| Write Pulse Width |
| 15 |
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| 20 |
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| ns | ||||||||||||||||
tSD |
| Data Setup to Write End |
| 15 |
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| 15 |
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tHD |
| Data Hold From Write End |
| 0 |
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| 0 |
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tHZWE[23, 24] |
| R/W | LOW to High Z |
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| 12 |
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| 15 | ns | |||||||||||||||
tLZWE[23, 24] |
| R/W | HIGH to Low Z |
| 3 |
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| 0 |
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tWDD[25] |
| Write Pulse to Data Delay |
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| 45 |
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| 50 | ns | ||||||||||||||||
tDDD[25] |
| Write Data Valid to Read Data Valid |
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| 30 |
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| 35 | ns | ||||||||||||||||
Busy Timing[26] |
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tBLA |
| BUSY | LOW from Address Match |
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| 20 |
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tBHA |
| BUSY | HIGH from Address Mismatch |
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| 20 |
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tBLC |
| BUSY | LOW from | CE |
| LOW |
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tBHC |
| BUSY | HIGH from | CE | HIGH |
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| 17 |
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| 17 | ns | |||||||||||||
tPS |
| Port Setup for Priority |
| 5 |
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| 5 |
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tWB |
| R/W | HIGH after BUSY (Slave) |
| 0 |
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| 0 |
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tWH |
| R/W | HIGH after | BUSY | HIGH (Slave) |
| 15 |
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| 17 |
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tBDD[27] |
| BUSY | HIGH to Data Valid |
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| 20 |
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| 25 | ns | |||||||||||||||
Interrupt Timing[26] |
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tINS |
| INT | Set Time |
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| 20 |
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tINR |
| INT | Reset Time |
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| 20 |
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Semaphore Timing |
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tSOP |
| SEM Flag Update Pulse | (OE | or | SEM) |
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| 10 |
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| 12 |
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tSWRD |
| SEM Flag Write to Read Time |
| 5 |
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tSPS |
| SEM Flag Contention Window |
| 5 |
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tSAA |
| SEM Address Access Time |
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| 20 |
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| 25 | ns | ||||||||||||||||
Data Retention Mode | Timing |
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The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV are designed for battery backup. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention:
1.Chip Enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2V.
2.CE must be kept between VCC – 0.2V and 70 percent of VCC during the power up and power down transitions.
3.The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (3.0V).
| Data Retention Mode | ||
VCC | 3.0V | VCC > 2.0V | 3.0V |
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CE | VCC to VCC – 0.2V |
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tRC
VIH 
Parameter | Test Conditions[28] | Max | Unit |
ICCDR1 | at VCCDR = 2V | 50 | μA |
Notes
25.For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12.
26.Test conditions used are Load 2.
27.tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).
28.CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document #: | Page 10 of 19 |
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