Cypress CY7C026AV, CY7C024AV, CY7C024BV, CY7C0251AV manual CER ValidFirst, Right Address Valid First

Page 15

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Switching Waveforms (continued)

Figure 14. Busy Timing Diagram No.1 (CE Arbitration)[48]

CELValid First

ADDRESS L,R

CEL

CER

BUSYR

CER ValidFirst:

ADDRESSL,R

CER

CE L

BUSYL

ADDRESS MATCH

tPS

 

 

 

tBLC

 

 

 

 

 

 

 

tBHC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDRESS MATCH

 

tPS

 

tBLC

tBHC

Figure 15. Busy Timing Diagram No.2 (Address Arbitration)[48]

Left Address Valid First:

ADDRESSL

ADDRESSR

BUSY R

tRC or tWC

ADDRESS MATCH

 

ADDRESS MISMATCH

 

tPS

 

 

tBLA

 

 

 

 

tBHA

 

 

 

 

 

 

 

 

 

 

 

 

 

Right Address Valid First:

ADDRESSR

ADDRESSL

BUSY L

tRC or tWC

ADDRESS MATCH

 

ADDRESS MISMATCH

 

tPS

 

 

tBLA

 

 

 

 

 

 

 

tBHA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

48. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.

Document #: 38-06052 Rev. *J

Page 15 of 19

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Contents Features Logic Block DiagramCypress Semiconductor Corporation 198 Champion Court Pin Tqfp Top View Pin ConfigurationsCY7C0241AV 4K × Maximum Access Time Typical Operating Current Selection GuideParameter CY7C024AV/024BV/025AV/026AV Unit Pin Definitions ArchitectureFunctional Description Busy Master/SlaveSemaphore Operation Left Port Right Port Function Non-Contending Read/Write Inputs Outputs OperationIO 0 -IO Interrupt Operation Example assumes = HighCapacitance Electrical CharacteristicsMaximum Ratings Operating RangeRead Cycle Switching CharacteristicsALL Inputpulses CY7C024AV/024BV/025AV/026AV Parameter DescriptionParameter Test Conditions Max Unit Data Retention Mode TimingParameter Description Busy Timing26Read Cycle No Either Port Address Access29, 30 Switching WaveformsWrite Cycle No R/W Controlled Timing 34, 35, 36 CY7C024AV/024BV/025AV/026AV Timing Diagram of Read with Busy M/S=HIGH47 Right Address Valid First CER ValidFirstRight Side Clears INT R Right Side Sets IntlLeft Side Clears INT L Ordering Information 16K x18 3.3V Asynchronous Dual-Port Sram Package DiagramSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History