Cypress CY7C025AV, CY7C024AV, CY7C026AV Document History, Sales, Solutions, and Legal Information

Page 19

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document History Page

Document Title: CY7C024AV/024BV/025AV/026AV, CY7C0241AV/0251AV/036AV 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

Document Number: 38-06052

Rev.

ECN No.

Orig. of

Submission

Description of Change

Change

Date

 

 

 

 

 

 

 

 

 

 

**

110204

SZV

11/11/01

Change from Spec number: 38-00838 to 38-06052

 

 

 

 

 

*A

122302

RBI

12/27/02

Power up requirements added to Maximum Ratings Information

 

 

 

 

 

*B

128958

JFU

9/03/03

Added CY7C025AV-25AI to Ordering Information

 

 

 

 

 

*C

237622

YDT

See ECN

Removed cross information from features section

 

 

 

 

 

*D

241968

WWZ

See ECN

Added CY7C024AV-25AI to Ordering Information

 

 

 

 

 

*E

276451

SPN

See ECN

Corrected x18 for 026AV to x16

 

 

 

 

 

*F

279452

RUY

See ECN

Added Pb-free packaging information

 

 

 

 

Corrected pin A113L to A13L on CY7C026AV pin list

 

 

 

 

Added minimum VIL of 0.3V and note 16

*G

373580

RUY

See ECN

Corrected CY7C024AC-25AXC to CY7C024AV-25AXC in Ordering Information

 

 

 

 

 

*H

380476

PCX

See ECN

Added to Part Ordering information:

 

 

 

 

CY7C024AV-15AI, CY7C024AV-15AXI, CY7C024AV-20AI,

 

 

 

 

CY7C024AV-20AXI, CY7C025AV-20AXI, CY7C026AV-20AXI

*I

2543577

NXR/AESA

07/25/08

Updated note number 33 on page 12 from “R/W

must be HIGH during all

 

 

 

 

address transitions” to “R/W or CE must be HIGH during all address transitions”

*J

2623540

VKN/PYRS

12/17/08

Added CY7C024BV part

 

 

 

 

 

 

 

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© Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 38-06052 Rev. *J

Revised December 10, 2008

Page 19 of 19

All products and company names mentioned in this document may be the trademarks of their respective holders.

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Image 19
Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation 198 Champion Court Pin Tqfp Top View Pin ConfigurationsCY7C0241AV 4K × Selection Guide Maximum Access Time Typical Operating CurrentParameter CY7C024AV/024BV/025AV/026AV Unit Architecture Pin DefinitionsFunctional Description Master/Slave BusySemaphore Operation Left Port Right Port Function Non-Contending Read/Write Inputs Outputs OperationIO 0 -IO Interrupt Operation Example assumes = HighCapacitance Electrical CharacteristicsMaximum Ratings Operating RangeRead Cycle Switching CharacteristicsALL Inputpulses CY7C024AV/024BV/025AV/026AV Parameter DescriptionParameter Test Conditions Max Unit Data Retention Mode TimingParameter Description Busy Timing26Read Cycle No Either Port Address Access29, 30 Switching WaveformsWrite Cycle No R/W Controlled Timing 34, 35, 36 CY7C024AV/024BV/025AV/026AV Timing Diagram of Read with Busy M/S=HIGH47 Right Address Valid First CER ValidFirstRight Side Sets Intl Right Side Clears INT RLeft Side Clears INT L Ordering Information 16K x18 3.3V Asynchronous Dual-Port Sram Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History