Cypress CY7C0241AV, CY7C026AV, CY7C024BV, CY7C0251AV, CY7C036AV manual CY7C024AV/024BV/025AV/026AV

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		CY7C024AV/024BV/025AV/026AV
		CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
	Figure 10. Semaphore Read After Write Timing, Either Side[43]
		tSAA	tOHA
A 0–A 2	VALID ADRESS	VALID ADRESS
	tAW	tACE
	tHA	tACE
SEM	tHA
SEM	tSCE	tSOP
	tSCE	tSOP
	tSD
IO 0	DATAIN VALID		DATAOUT VALID
	DATAIN VALID		DATAOUT VALID
tSA	tHD
tSA	tPWE
R/W
	tSWRD	tDOE
OE		tSOP
	WRITE CYCLE	READ CYCLE

Figure 11. Timing Diagram of Semaphore Contention[44, 45, 46]

A0L –A2L

R/WL

SEML

A0R–A2R

MATCH

tSPS

R/WR

Notes

43.CE = HIGH for the duration of the above timing (both write and read cycle).

44.IO0R = IO0L = LOW (request semaphore); CER = CEL = HIGH.

45.Semaphores are reset (available to both ports) at cycle start.

46.If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.

Document #: 38-06052 Rev. *J

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Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation 198 Champion Court Pin Tqfp Top View Pin ConfigurationsCY7C0241AV 4K × Selection Guide Maximum Access Time Typical Operating CurrentParameter CY7C024AV/024BV/025AV/026AV Unit Architecture Pin DefinitionsFunctional Description Master/Slave BusySemaphore Operation IO 0 -IO Non-Contending Read/Write Inputs Outputs OperationInterrupt Operation Example assumes = High Left Port Right Port FunctionMaximum Ratings Electrical CharacteristicsOperating Range CapacitanceALL Inputpulses Switching CharacteristicsCY7C024AV/024BV/025AV/026AV Parameter Description Read CycleParameter Description Data Retention Mode TimingBusy Timing26 Parameter Test Conditions Max UnitRead Cycle No Either Port Address Access29, 30 Switching WaveformsWrite Cycle No R/W Controlled Timing 34, 35, 36 CY7C024AV/024BV/025AV/026AV Timing Diagram of Read with Busy M/S=HIGH47 Right Address Valid First CER ValidFirstRight Side Sets Intl Right Side Clears INT RLeft Side Clears INT L Ordering Information 16K x18 3.3V Asynchronous Dual-Port Sram Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History