Cypress CY7C0251AV, CY7C024AV, CY7C026AV, CY7C024BV, CY7C036AV, CY7C025AV manual Ordering Information

Page 17

CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Ordering Information

4K x16 3.3V Asynchronous Dual-Port SRAM

Speed

Ordering Code

Package

Package Type

Operating

(ns)

Diagram

Range

15

CY7C024AV-15AI

51-85048

100-Pin Thin Quad Flat Pack

Industrial

 

 

 

 

 

 

CY7C024BV-15AXI

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

 

 

 

 

 

 

20

CY7C024AV-20AC

51-85048

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C024AV-20AXC

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

 

 

 

 

 

 

 

CY7C024AV-20AI

51-85048

100-Pin Thin Quad Flat Pack

Industrial

 

 

 

 

 

 

CY7C024AV-20AXI

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

 

 

 

 

 

 

25

CY7C024AV-25AC

51-85048

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C024AV-25AXC

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

 

 

 

 

 

 

 

CY7C024AV-25AI

51-85048

100-Pin Thin Quad Flat Pack

Industrial

 

 

 

 

 

 

CY7C024AV-25AXI

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

 

 

 

 

 

 

8K x16 3.3V Asynchronous Dual-Port SRAM

 

 

Speed

Ordering Code

Package

Package Type

Operating

(ns)

Name

Range

20

CY7C025AV-20AC

51-85048

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C025AV-20AXC

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

 

 

 

 

 

 

 

CY7C025AV-20AXI

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

Industrial

 

 

 

 

 

25

CY7C025AV-25AC

51-85048

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C025AV-25AXC

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

 

 

 

 

 

 

 

CY7C025AV-25AI

51-85048

100-Pin Thin Quad Flat Pack

Industrial

 

 

 

 

 

 

CY7C025AV-25AXI

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

 

 

 

 

 

 

16K x16 3.3V Asynchronous Dual-Port SRAM

 

 

Speed

Ordering Code

Package

Package Type

Operating

(ns)

Name

Range

20

CY7C026AV-20AC

51-85048

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C026AV-20AXC

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

 

 

 

 

 

 

 

CY7C026AV-20AXI

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

Industrial

 

 

 

 

 

25

CY7C026AV-25AC

51-85048

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C026AV-25AXC

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

 

 

 

 

 

 

 

CY7C026AV-25AI

51-85048

100-Pin Thin Quad Flat Pack

Industrial

 

 

 

 

 

 

CY7C026AV-25AXI

51-85048

100-Pin Pb-Free Thin Quad Flat Pack

 

 

 

 

 

 

4K x18 3.3V Asynchronous Dual-Port SRAM

 

 

Speed

Ordering Code

Package

Package Type

Operating

 

(ns)

Name

Range

 

20

CY7C0241AV-20AC

51-85048

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

 

25

CY7C0241AV-25AC

51-85048

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

 

8K x18 3.3V Asynchronous Dual-Port SRAM

 

 

 

 

 

 

 

 

 

Speed

Ordering Code

Package

Package Type

Operating

 

(ns)

Name

Range

 

20

CY7C0251AV-20AC

51-85048

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

 

25

CY7C0251AV-25AC

51-85048

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

 

Document #: 38-06052 Rev. *J

 

 

Page 17 of 19

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Pin Tqfp Top View Pin ConfigurationsCY7C0241AV 4K × Parameter CY7C024AV/024BV/025AV/026AV Unit Maximum Access Time Typical Operating CurrentSelection Guide Functional Description Pin DefinitionsArchitecture Semaphore Operation BusyMaster/Slave IO 0 -IO Non-Contending Read/Write Inputs Outputs OperationInterrupt Operation Example assumes = High Left Port Right Port FunctionMaximum Ratings Electrical CharacteristicsOperating Range CapacitanceALL Inputpulses Switching CharacteristicsCY7C024AV/024BV/025AV/026AV Parameter Description Read CycleParameter Description Data Retention Mode TimingBusy Timing26 Parameter Test Conditions Max UnitRead Cycle No Either Port Address Access29, 30 Switching WaveformsWrite Cycle No R/W Controlled Timing 34, 35, 36 CY7C024AV/024BV/025AV/026AV Timing Diagram of Read with Busy M/S=HIGH47 Right Address Valid First CER ValidFirstLeft Side Clears INT L Right Side Clears INT RRight Side Sets Intl Ordering Information 16K x18 3.3V Asynchronous Dual-Port Sram Package DiagramDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions