Cypress CY7C036AV, CY7C024AV, CY7C026AV Package Diagram, 16K x18 3.3V Asynchronous Dual-Port Sram

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CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

16K x18 3.3V Asynchronous Dual-Port SRAM

Speed	Ordering Code	Package	Package Type	Operating
(ns)	Ordering Code	Name	Package Type	Range
20	CY7C036AV-20AC	51-85048	100-Pin Thin Quad Flat Pack	Commercial

25	CY7C036AV-25AC	51-85048	100-Pin Thin Quad Flat Pack	Commercial

	CY7C036AV-25AXC	51-85048	100-Pin Pb-free Thin Quad Flat Pack

	CY7C036AV-25AI	51-85048	100-Pin Thin Quad Flat Pack	Industrial

51-85048 *C

Document #: 38-06052 Rev. *J

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Contents Features Logic Block DiagramCypress Semiconductor Corporation 198 Champion Court Pin Configurations Pin Tqfp Top ViewCY7C0241AV 4K × Maximum Access Time Typical Operating Current Selection GuideParameter CY7C024AV/024BV/025AV/026AV Unit Pin Definitions ArchitectureFunctional Description Busy Master/SlaveSemaphore Operation Interrupt Operation Example assumes = High Non-Contending Read/Write Inputs Outputs OperationIO 0 -IO Left Port Right Port FunctionOperating Range Electrical CharacteristicsMaximum Ratings CapacitanceCY7C024AV/024BV/025AV/026AV Parameter Description Switching CharacteristicsALL Inputpulses Read CycleBusy Timing26 Data Retention Mode TimingParameter Description Parameter Test Conditions Max UnitSwitching Waveforms Read Cycle No Either Port Address Access29, 30Write Cycle No R/W Controlled Timing 34, 35, 36 CY7C024AV/024BV/025AV/026AV Timing Diagram of Read with Busy M/S=HIGH47 CER ValidFirst Right Address Valid FirstRight Side Clears INT R Right Side Sets IntlLeft Side Clears INT L Ordering Information Package Diagram 16K x18 3.3V Asynchronous Dual-Port SramSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History