Cypress CY7C024AV, CY7C026AV, CY7C024BV, CY7C0251AV Timing Diagram of Read with Busy M/S=HIGH47

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CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Switching Waveforms (continued)

Figure 12. Timing Diagram of Read with BUSY (M/S=HIGH)[47]

	tWC
ADDRESSR	MATCH
R/WR	tPWE
	tSD	tHD
DATA INR	VALID
	tPS
ADDRESSL	MATCH
	tBLA	tBHA
BUSYL		tBDD
		tDDD
DATAOUTL		VALID
	tWDD

Figure 13. Write Timing with Busy Input (M/S=LOW)

R/W

BUSY

tWB

tPWE

tWH

Note

47. CEL = CER = LOW.

Document #: 38-06052 Rev. *J

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Pin Configurations Pin Tqfp Top ViewCY7C0241AV 4K × Parameter CY7C024AV/024BV/025AV/026AV Unit Maximum Access Time Typical Operating CurrentSelection Guide Functional Description Pin DefinitionsArchitecture Semaphore Operation BusyMaster/Slave Interrupt Operation Example assumes = High Non-Contending Read/Write Inputs Outputs OperationIO 0 -IO Left Port Right Port FunctionOperating Range Electrical CharacteristicsMaximum Ratings CapacitanceCY7C024AV/024BV/025AV/026AV Parameter Description Switching CharacteristicsALL Inputpulses Read CycleBusy Timing26 Data Retention Mode TimingParameter Description Parameter Test Conditions Max UnitSwitching Waveforms Read Cycle No Either Port Address Access29, 30Write Cycle No R/W Controlled Timing 34, 35, 36 CY7C024AV/024BV/025AV/026AV Timing Diagram of Read with Busy M/S=HIGH47 CER ValidFirst Right Address Valid FirstLeft Side Clears INT L Right Side Clears INT RRight Side Sets Intl Ordering Information Package Diagram 16K x18 3.3V Asynchronous Dual-Port SramDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions