Cypress CY62157E manual Product Portfolio, Tsop Vfbga

Page 2

 

 

 

 

 

 

 

 

CY62157E MoBL®

Pin Configuration[2, 3]

 

 

 

 

 

 

 

 

 

 

 

 

 

TSOP II

 

 

 

 

VFBGA

 

 

 

 

Top View

 

 

 

 

Top View

 

 

 

A4

1

44

A5

1

2

3

4

5

6

 

 

 

 

 

 

 

 

 

A3

2

43

A6

BLE

OE

A0

A1

A2

CE2

A

A

3

42

A

2

7

 

 

 

 

 

 

 

 

A1

4

41

OE

 

 

 

 

 

 

 

 

A0

5

40

BHE

IO8

BHE

A3

A4

CE1

IO0

B

CE

6

39

BLE

 

 

 

 

 

 

 

 

IO0

7

38

IO15

IO 9

IO10

A5

A6

IO1

IO2

C

IO1

8

37

IO14

IO2

9

36

IO13

VSS

IO

A17

A7

IO

Vcc

D

IO

10

35

IO

3

 

12

 

 

11

 

 

3

 

 

VCC

11

34

VSS

 

 

 

 

 

 

 

 

VSS

12

33

VCC

V

IO

 

NC

A

IO4

Vss

E

IO4

13

32

IO

CC

 

12

 

16

 

 

IO5

14

31

IO1110

IO 14

IO13

A14

A15

IO5

IO6

F

IO6

15

30

IO9

IO7

16

29

IO

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

WE

17

28

A8

IO 15

NC

A12

A13

WE

IO7

G

A18

18

27

A9

 

 

 

 

 

 

 

 

A17

19

26

A10

A18

A8

A9

A10

A11

NC

H

A16

20

25

A11

A15

21

24

A12

 

 

 

 

 

 

 

 

A14

22

23

A13

 

 

 

 

 

 

 

 

Product Portfolio

 

 

 

 

 

 

 

 

 

 

 

Power Dissipation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Speed

 

Operating

ICC, (mA)

 

 

Standby, I

 

 

 

VCC Range (V)

 

(ns)

f = 1MHz

f = fmax

 

(A)

SB2

Product

Range

Min

 

Typ[4]

 

Max

 

Typ[4]

 

Max

Typ[4]

 

Max

 

Typ[4]

 

Max

CY62157E-45

Ind’l

4.5

 

5.0

 

5.5

45

1.8

 

3

18

 

25

 

2

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY62157E-55[5]

Auto

4.5

 

5.0

 

5.5

55

1.8

 

4

18

 

35

 

2

 

30

Notes:

2.NC pins are not connected on the die.

3.The 44-pin TSOP II package has only one chip enable (CE) pin.

4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.

5.Automotive product information is Preliminary.

Document #: 38-05695 Rev. *C

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Contents Functional Description1 FeaturesLogic Block Diagram Cypress Semiconductor CorporationProduct Portfolio Tsop VfbgaOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Capacitance9AC Test Loads and Waveforms Data Retention Characteristics Over the Operating RangeThermal Resistance9 Data Retention Waveform11Min Max Unit Read Cycle Switching Characteristics Over the Operating Range45 ns 55 ns Parameter Description Min Write CycleRead Cycle 2 OE Controlled17 Switching WaveformsRead Cycle 1 Address Transition Controlled16 50%Write Cycle 1 WE Controlled 15, 19, 20 Write Cycle 2 CE 1 or CE 2 Controlled 15, 19, 20Write Cycle 3 WE Controlled, OE LOW20 Write Cycle 4 BHE/BLE Controlled, OE LOW20Ordering Information Inputs/Outputs Mode PowerTruth Table BHE BLEPackage Diagrams Pin Tsop IIBall Vfbga 6 x 8 x 1 mm REV ECN no Issue Date Orig. Description of ChangeDocument History