Cypress CY62157E manual Write Cycle 1 WE Controlled 15, 19, 20

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CY62157E MoBL®

Write Cycle 1 (WE Controlled)[15, 19, 20, 21]
		tWC
ADDRESS
CE1		tSCE
CE1
CE2
	tAW	tPWE	tHA
WE	tSA	tPWE
WE
BHE/BLE		tBW
OE
		tSD	tHD
DATA IO	See Note 21	VALID DATA
	tHZOE
Write Cycle 2 (CE1 or CE2 Controlled)[15, 19, 20, 21]

19.Data IO is high impedance if OE = VIH.

20.If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.

21.During this period, the IOs are in output state and input signals should not be applied.

Document #: 38-05695 Rev. *C

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram Functional Description1Tsop Vfbga Product PortfolioCapacitance9 Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeData Retention Waveform11 Data Retention Characteristics Over the Operating RangeThermal Resistance9 AC Test Loads and WaveformsWrite Cycle Switching Characteristics Over the Operating Range45 ns 55 ns Parameter Description Min Min Max Unit Read Cycle50% Switching WaveformsRead Cycle 1 Address Transition Controlled16 Read Cycle 2 OE Controlled17Write Cycle 2 CE 1 or CE 2 Controlled 15, 19, 20 Write Cycle 1 WE Controlled 15, 19, 20Write Cycle 4 BHE/BLE Controlled, OE LOW20 Write Cycle 3 WE Controlled, OE LOW20BHE BLE Inputs/Outputs Mode PowerTruth Table Ordering InformationPin Tsop II Package DiagramsBall Vfbga 6 x 8 x 1 mm Document History Issue Date Orig. Description of ChangeREV ECN no

Write Cycle 1 (WE Controlled)[15, 19, 20, 21]