Cypress CY62157E Thermal Resistance9, AC Test Loads and Waveforms, Data Retention Waveform11

Page 4

CY62157E MoBL®

Thermal Resistance[9]

Parameter

Description

Test Conditions

TSOP II

VFBGA

Unit

ΘJA

Thermal Resistance

Still Air, soldered on a 3 × 4.5 inch,

77

72

°C/W

 

(Junction to Ambient)

two-layer printed circuit board

 

 

 

ΘJC

Thermal Resistance

 

13

8.86

°C/W

 

(Junction to Case)

 

 

 

 

AC Test Loads and Waveforms

R1

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

 

3V

 

 

 

 

 

 

 

 

ALL INPUT PULSES

 

 

 

 

 

 

 

 

 

 

 

90%

 

10%

 

 

 

 

 

 

90%

 

 

 

 

 

10%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R2

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise Time = 1 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

Fall Time = 1 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

Equivalent to: THEVENIN EQUIVALENT

RTH

OUTPUT V

Parameters

Values

Unit

R1

1800

 

 

 

R2

990

 

 

 

RTH

639

VTH

1.77

V

Data Retention Characteristics (Over the Operating Range)

Parameter

Description

 

 

Conditions

 

Min

Typ[4]

Max

Unit

VDR

VCC for Data Retention

 

 

 

 

 

2

 

 

V

ICCDR

Data Retention Current

VCC=2V,

 

1> VCC – 0.2V,

Industrial

 

 

 

8

A

CE

 

 

 

CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V

 

 

 

 

 

 

 

 

Automotive

 

 

 

30

 

tCDR[9]

Chip Deselect to Data

 

 

 

 

 

0

 

 

ns

 

Retention Time

 

 

 

 

 

 

 

 

 

t [10]

Operation Recovery Time

 

 

 

 

t

RC

 

 

ns

R

 

 

 

 

 

 

 

 

 

Data Retention Waveform[11]

DATA RETENTION MODE

VCC

VCC(min)

VDR > 2 V

VCC(min)

CE1or

tCDR

 

tR

 

 

 

BHE.BLE

 

 

 

CE2

 

 

 

Notes:

10.Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.

11.BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.

Document #: 38-05695 Rev. *C

Page 4 of 12

[+] Feedback

Image 4
Contents Features Logic Block DiagramFunctional Description1 Cypress Semiconductor CorporationProduct Portfolio Tsop VfbgaElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range Capacitance9Data Retention Characteristics Over the Operating Range Thermal Resistance9AC Test Loads and Waveforms Data Retention Waveform11Switching Characteristics Over the Operating Range 45 ns 55 ns Parameter Description MinMin Max Unit Read Cycle Write CycleSwitching Waveforms Read Cycle 1 Address Transition Controlled16Read Cycle 2 OE Controlled17 50%Write Cycle 1 WE Controlled 15, 19, 20 Write Cycle 2 CE 1 or CE 2 Controlled 15, 19, 20Write Cycle 3 WE Controlled, OE LOW20 Write Cycle 4 BHE/BLE Controlled, OE LOW20Inputs/Outputs Mode Power Truth TableOrdering Information BHE BLEPackage Diagrams Pin Tsop IIBall Vfbga 6 x 8 x 1 mm Document History Issue Date Orig. Description of ChangeREV ECN no