Cypress CY62157E manual Switching Waveforms, Read Cycle 1 Address Transition Controlled16, 50%

Page 6

CY62157E MoBL®

Switching Waveforms

Read Cycle 1 (Address Transition Controlled)[16, 17]

tRC

ADDRESS

tOHA tAA

DATA OUT

PREVIOUS DATA VALID

 

 

 

 

DATA VALID

 

 

 

Read Cycle 2 (OE Controlled)[17, 18]

ADDRESS

 

 

 

CE1

 

 

tRC

 

 

 

tPD

CE2

 

tACE

tHZCE

 

 

BHE/BLE

 

 

 

 

 

tDBE

t

 

 

tLZBE

HZBE

OE

 

 

 

 

 

 

 

tDOE

tHZOE

 

 

tLZOE

HIGH

DATA OUT

HIGH IMPEDANCE

IMPEDANCE

 

tLZCE

DATA VALID

VCC

tPU

ICC

50%

SUPPLY

 

50%

CURRENT

 

 

ISB

Notes:

16.The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.

17.WE is HIGH for read cycle.

18.Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.

Document #: 38-05695 Rev. *C

Page 6 of 12

[+] Feedback

Image 6
Contents Functional Description1 FeaturesLogic Block Diagram Cypress Semiconductor CorporationProduct Portfolio Tsop VfbgaOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Capacitance9AC Test Loads and Waveforms Data Retention Characteristics Over the Operating RangeThermal Resistance9 Data Retention Waveform11Min Max Unit Read Cycle Switching Characteristics Over the Operating Range45 ns 55 ns Parameter Description Min Write CycleRead Cycle 2 OE Controlled17 Switching WaveformsRead Cycle 1 Address Transition Controlled16 50%Write Cycle 1 WE Controlled 15, 19, 20 Write Cycle 2 CE 1 or CE 2 Controlled 15, 19, 20Write Cycle 3 WE Controlled, OE LOW20 Write Cycle 4 BHE/BLE Controlled, OE LOW20Ordering Information Inputs/Outputs Mode PowerTruth Table BHE BLEPackage Diagrams Pin Tsop IIBall Vfbga 6 x 8 x 1 mm Issue Date Orig. Description of Change Document HistoryREV ECN no