Cypress CY62157CV30, CY62157CV33 Switching Characteristics Over the Operating Range, Write Cycle

CY62157CV30/33

Switching Characteristics Over the Operating Range [10]

							70 ns
Parameter					Description				Unit
						Min.		Max.
Read Cycle
tRC	Read Cycle Time					70			ns
tAA	Address to Data Valid							70	ns
tOHA	Data Hold from Address Change					10			ns
tACE		1 LOW and CE2 HIGH to Data Valid						70	ns
	CE
tDOE			LOW to Data Valid					35	ns
	OE
t			LOW to Low-Z[11]			5			ns
	OE
LZOE
tHZOE			HIGH to High-Z[11, 12]					25	ns
	OE
tLZCE		1 LOW and CE2 HIGH to Low-Z[11]				10			ns
	CE
t				HIGH or CE	LOW to High-Z[11, 12]			25	ns
	CE	1
HZCE					2
tPU		1 LOW and CE2 HIGH to Power-up				0			ns
	CE
tPD		1 HIGH or CE2 LOW to Power-down						70	ns
	CE
tDBE								70	ns
	BHE/BLE LOW to Data Valid
tLZBE[11]						5			ns
	BHE/BLE LOW to Low-Z[13]
tHZBE								25	ns
	BHE/BLE HIGH to High-Z[11, 12]
Write Cycle[14]
tWC	Write Cycle Time					70			ns
tSCE		1 LOW and CE2 HIGH to Write End				60			ns
	CE
tAW	Address Set-up to Write End					60			ns
tHA	Address Hold from Write End					0			ns
tSA	Address Set-up to Write Start					0			ns
tPWE			Pulse Width			50			ns
	WE
tBW						60			ns
	BHE/BLE Pulse Width
tSD	Data Set-up to Write End					30			ns
tHD	Data Hold from Write End					0			ns
t			LOW to High-Z[11, 12]					25	ns
	WE
HZWE
tLZWE			HIGH to Low-Z[11]			5			ns
	WE

Notes:

10.Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30-pF load capacitance.

11.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

12.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.

13.When both byte enables are toggled together this value is 10 ns.

14.The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. All signals must be ACTIVE to initiate a Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the Write.

Document #: 38-05014 Rev. *F Page 6 of 13

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