Cypress CY14B101Q2, CY14B101Q3, CY14B101Q1 manual NvSRAM Special Instructions, Software Store

Page 11

CY14B101Q1

CY14B101Q2

PRELIMINARYCY14B101Q3

Figure 12. Burst Mode Read Instruction Timing

CS

SCK

SI

SO

0

1

 

2

3

4

5

6

7

0

1

2

3

4

5

6

7

 

20

21

22

23

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7

0

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7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

~~

 

 

 

 

 

 

 

 

 

 

 

 

~

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

~

 

 

 

 

 

 

 

 

 

 

 

Op-Code

 

 

 

 

 

 

 

 

 

 

17-bit Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

 

0

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1

1

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A16

 

A3

A2

A1

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSB

 

 

 

 

 

~~

 

 

LSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Byte 1

 

 

 

 

 

 

 

Data Byte N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D7

D6 D5 D4

D3 D2

D1 D0

D7 D0

D7

D6

D5 D4

D3 D2

D1 D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSB

 

 

 

 

LSB

~~

MSB

 

 

 

 

LSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CS

SCK

SI

SO

Figure 13. Write Instruction Timing

0

1

2

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4

5

6

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0

1

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6

7

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23

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~~

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Op-Code

 

 

 

 

 

 

 

 

 

17-bit Address

 

 

 

 

 

 

 

 

 

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

A16

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

 

 

 

 

 

 

 

 

MSB

 

 

 

 

 

 

~ ~

 

 

 

LSB MSB

 

 

Data

 

 

LSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HI-Z

 

 

 

 

 

 

 

 

 

 

 

 

 

CS

SCK

SI

SO

Figure 14. Burst Mode Write Instruction Timing

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

20

21

22

23

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2

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4

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7

0

 

7

0

1

2

3

4

5

6

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

~~

 

 

 

 

 

 

 

 

 

 

 

~

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Byte 1

 

 

 

~

 

 

Data Byte N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Op-Code

 

 

 

 

 

 

 

 

 

 

17-bit Address

 

 

 

 

 

 

 

 

~~

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

~ ~

 

 

 

 

D6 D5 D4

 

 

 

 

 

 

D6 D5

D4

 

 

 

 

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

A16

A3

A2

A1 A0

D7

D3 D2

D1

D0 D7

D0

D7

D3 D2

D1

D0

 

 

 

 

 

 

 

 

MSB

 

 

 

 

 

 

 

 

 

 

LSB MSB

 

 

 

 

 

LSB

 

 

 

 

 

 

 

 

 

 

HI-Z

nvSRAM Special Instructions

CY14B101Q1/CY14B101Q2/CY14B101Q3 provides four special instructions which enables access to four nvSRAM specific functions: STORE, RECALL, ASDISB, and ASENB. Table 8 lists these instructions.

Software STORE

When a STORE instruction is executed, nvSRAM performs a Software STORE operation. The STORE operation is issued irrespective of whether a write has taken place since last STORE or RECALL operation.

Document #: 001-50091 Rev. *A

Table 8. nvSRAM Special Instructions

Function Name

Opcode

Operation

STORE

0011 1100

Software STORE

 

 

 

RECALL

0110 0000

Software RECALL

 

 

 

ASENB

0101 1001

AutoStore Enable

 

 

 

ASDISB

0001 1001

AutoStore Disable

 

 

 

To issue this instruction, the device must be write enabled (WEN bit = ‘1’). The instruction is performed by transmitting the STORE opcode on the SI pin following the falling edge of CS. The WEN

Page 11 of 22

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Contents Mbit NonVolatile Sram Internally organized as 128K x FeaturesLogic Block Diagram Functional OverviewHold PinoutsPin Definitions Pin Name Type Description Store Operation Device OperationSram Write Sram ReadRecall Operation Hardware Recall Power UpSoftware Store Operation Hardware Store and HSB pin OperationSPI Overview Serial Peripheral InterfaceSPI Modes System Configuration Using SPI nvSRAMSPI Functional Description SPI Operating FeaturesWrite Status Register Wrsr Instruction Status RegisterRead Status Register Rdsr Instruction Block Protection Write Enable Wren InstructionWrite Disable Wrdi Instruction Write Protection and Block ProtectionWrite Sequence Write Memory AccessWrite Protect WP Pin Read Sequence ReadNvSRAM Special Instructions Function Name Opcode Operation NvSRAM Special InstructionsSoftware Store Hold Pin Operation AutoStore Disable AsdisbAutoStore Enable Asenb Parameter Description Test Conditions Min Max Unit DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceCypress Alt Description 40MHz Unit Parameter Min Max AC Switching CharacteristicsParameters Description CY‘4B101QxA Unit Min Max AutoStore or Power Up RecallSwitching Waveforms Soft Sequence Processing Time 100 Software Controlled Store and Recall CyclesParameter Description CY14B101Q1 Unit Min Max Recall Duration 200Hardware Store Pulse Width To Output Active Time when write latch not setHardware Store Cycle Parameter Description CY14B101Q1 Unit MinCY 14 B 101 Q 1-SF X C T Ordering Code Package Package Type Operating Diagram RangeOrdering Information Part Numbering NomenclaturePin 300 mil DFN Package Package DiagramsPin 300 mil Soic REV ECN no Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History