Cypress CY14B101Q3 manual AutoStore Disable Asdisb, AutoStore Enable Asenb, Hold Pin Operation

Page 12

CY14B101Q1

CY14B101Q2

PRELIMINARYCY14B101Q3

bit is cleared on the positive edge of CS following the STORE instruction.

Figure 15. Software STORE Operation

CS

 

 

 

 

 

 

 

 

 

0

1

2

3

4

5

6

7

SCK

 

 

 

 

 

 

 

 

SI

0

0

1

1

1

1

0

0

SO

 

 

 

Hi-Z

 

 

 

 

 

 

 

 

 

 

 

Software RECALL

When a RECALL instruction is executed, nvSRAM performs a Software RECALL operation. To issue this instruction, the device must be write enabled (WEN = ‘1’).

The instruction is performed by transmitting the RECALL opcode on the SI pin following the falling edge of CS. The WEN bit is cleared on the positive edge of CS following the RECALL instruction.

Figure 16. Software RECALL Operation

CS

 

 

 

 

 

 

 

 

 

0

1

2

3

4

5

6

7

SCK

 

 

 

 

 

 

 

 

SI

0

1

1

0

0

0

0

0

SO

 

 

 

Hi-Z

 

 

 

 

 

 

 

 

 

 

 

AutoStore Disable (ASDISB)

AutoStore is enabled by default in CY14B101Q2/CY14B101Q3. The ASDISB instruction disables the AutoStore. This setting is not nonvolatile and needs to be followed by a STORE sequence to survive the power cycle.

To issue this instruction, the device must be write enabled (WEN

=‘1’). The instruction is performed by transmitting the ASDISB opcode on the SI pin following the falling edge of CS. The WEN bit is cleared on the positive edge of CS following the ASDISB instruction.

Figure 17. AutoStore Disable Operation

CS

 

 

 

 

 

 

 

 

 

0

1

2

3

4

5

6

7

SCK

 

 

 

 

 

 

 

 

SI

0

0

0

1

1

0

0

1

SO

 

 

 

Hi-Z

 

 

 

 

 

 

 

 

 

 

 

AutoStore Enable (ASENB)

The AutoStore Enable instruction enables the AutoStore on CY14B101Q1. This setting is not nonvolatile and needs to be followed by a STORE sequence to survive the power cycle.

To issue this instruction, the device must be write enabled (WEN

=‘1’). The instruction is performed by transmitting the ASENB opcode on the SI pin following the falling edge of CS. The WEN bit is cleared on the positive edge of CS following the ASENB instruction.

Note If ASDISB and ASENB instructions are executed in CY14B101Q1, the device is busy for the duration of software sequence processing time (tSS). However, ASDISB and ASENB instructions have no effect on CY14B101Q1 as AutoStore is internally disabled.

Figure 18. AutoStore Enable Operation

CS

 

 

 

 

 

 

 

 

 

0

1

2

3

4

5

6

7

SCK

 

 

 

 

 

 

 

 

SI

0

1

0

1

1

0

0

1

 

SO

 

 

 

Hi-Z

 

 

 

 

 

 

 

 

 

 

 

HOLD Pin Operation

The HOLD pin is used to pause the serial communication. When the device is selected and a serial sequence is underway, HOLD is used to pause the serial communication with the master device without resetting the ongoing serial sequence. To pause, the HOLD pin must be brought LOW when the SCK pin is LOW. To resume serial communication, the HOLD pin must be brought HIGH when the SCK pin is LOW (SCK may toggle during HOLD). While the device serial communication is paused, inputs to the SI pin are ignored and the SO pin is in the high impedance state.

This pin can be used by the master with the CS pin to pause the serial communication by bringing the pin HOLD LOW and deselecting an SPI slave to establish communication with another slave device, without the serial communication being reset. The communication may be resumed at a later point by selecting the device and setting the HOLD pin HIGH.

Figure 19. HOLD Operation

CS

~~

SCK

~~

HOLD

 

SO

 

Document #: 001-50091 Rev. *A

Page 12 of 22

[+] Feedback

Image 12
Contents Features Logic Block DiagramFunctional Overview Mbit NonVolatile Sram Internally organized as 128K xPinouts Pin Definitions Pin Name Type DescriptionHold Device Operation Sram WriteSram Read Store OperationHardware Recall Power Up Software Store OperationHardware Store and HSB pin Operation Recall OperationSerial Peripheral Interface SPI OverviewSystem Configuration Using SPI nvSRAM SPI ModesSPI Operating Features SPI Functional DescriptionStatus Register Read Status Register Rdsr InstructionWrite Status Register Wrsr Instruction Write Enable Wren Instruction Write Disable Wrdi InstructionWrite Protection and Block Protection Block ProtectionMemory Access Write Protect WP PinRead Sequence Read Write Sequence WriteNvSRAM Special Instructions Software StoreNvSRAM Special Instructions Function Name Opcode Operation AutoStore Disable Asdisb AutoStore Enable AsenbHold Pin Operation DC Electrical Characteristics Maximum RatingsOperating Range Parameter Description Test Conditions Min Max UnitData Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsAC Switching Characteristics Cypress Alt Description 40MHz Unit Parameter Min MaxAutoStore or Power Up Recall Switching WaveformsParameters Description CY‘4B101QxA Unit Min Max Software Controlled Store and Recall Cycles Parameter Description CY14B101Q1 Unit Min MaxRecall Duration 200 Soft Sequence Processing Time 100To Output Active Time when write latch not set Hardware Store CycleParameter Description CY14B101Q1 Unit Min Hardware Store Pulse WidthOrdering Code Package Package Type Operating Diagram Range Ordering InformationPart Numbering Nomenclature CY 14 B 101 Q 1-SF X C TPackage Diagrams Pin 300 mil DFN PackagePin 300 mil Soic Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History REV ECN no