CY62147DV30
4-Mbit (256K x 16) Static RAM
Features
•Temperature Ranges
—Industrial:
—
—
•Very high speed: 45 ns
•Wide voltage range:
•
•
—Typical active current: 1.5 mA @ f = 1 MHz
—Typical active current: 8 mA @ f = fmax
•Ultra low standby power
•Easy memory expansion with CE, and OE features
•Automatic
•CMOS for optimum speed/power
•Available in
•Byte
Functional Description[1]
The CY62147DV30 is a
vanced circuit design to provide
Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.
The CY62147DV30 is available in a
Logic Block Diagram
A10
A9
A8 |
|
| DECODER | ||
|
| ||||
A4 |
| ||||
A7 |
|
| |||
A6 |
|
| |||
A5 |
| ROW | |||
| |||||
A3 |
|
|
| ||
|
|
| |||
A2 |
|
|
| ||
|
|
| |||
A1 |
|
| |||
|
| ||||
A0 |
|
| |||
|
|
DATA IN DRIVERS
256K x 16 RAM Array
SENSE AMPS
Power
Circuit
Note:
COLUMN DECODER
| 11 | 12 | 13 | 14 | 15 | 16 | 17 | ||||||||
| A |
| A | A | A A A | A | |||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| CE |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
| BHE |
| |||
|
|
|
|
|
|
|
|
|
|
|
| BLE |
| ||
|
|
|
|
|
|
|
|
|
|
|
BHE WE CE
OE
BLE
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation | • | 198 Champion Court • San Jose, CA | • | |
Document #: |
| Revised August 31, 2006 |
[+] Feedback