Cypress CY62147DV30 manual Document History, REV ECN no, Issue Date Orig. Description of Change

Page 12

CY62147DV30

Document History Page

Document Title:CY62147DV30 MoBL® 4-Mbit (256K x 16) Static RAM

Document Number: 38-05340

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

127481

06/17/03

HRT

New Data Sheet

 

 

 

 

 

*A

131010

01/23/04

CBD

Changed from Advance to Preliminary

 

 

 

 

 

*B

213252

See ECN

AJU

Changed from Preliminary to Final

 

 

 

 

Added 70 ns speed bin

 

 

 

 

Modified footnote 7 to include ramp time and wait time

 

 

 

 

Modified input and output capacitance values to 10 pF

 

 

 

 

Modified Thermal Resistance values on page 4

 

 

 

 

Added “Byte power-down feature” in the features section

 

 

 

 

Modified Ordering Information for Pb-free parts

*C

257349

See ECN

PCI

Modified ordering information for 70-ns Speed Bin

 

 

 

 

 

*D

316039

See ECN

PCI

Added 45-ns Speed Bin in AC, DC and Ordering Information tables

 

 

 

 

Added Footnote #10 on page #4

 

 

 

 

Added Pb-free package ordering information on page # 9

 

 

 

 

Changed 44-lead TSOP-II package name on page 11 from Z44 to ZS44

 

 

 

 

Standardized Icc values across ‘L’ and ‘LL’ bins

*E

330365

See ECN

AJU

Added Automotive product information

 

 

 

 

 

*F

498575

See ECN

NXR

Added Automotive-A range

 

 

 

 

Added note# 9 on page# 3

 

 

 

 

Updated ordering information table

Document #: 38-05340 Rev. *F

Page 12 of 12

[+] Feedback

Image 12
Contents Features Logic Block DiagramFunctional Description1 Cypress Semiconductor CorporationPin Configuration2, 3 Product PortfolioElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range Data Retention Characteristics Over the Operating Range Thermal Resistance10AC Test Loads and Waveforms10 Data Retention Waveform13Switching Characteristics Over the Operating Range14 45 ns 55 ns 70 ns Parameter Description MinMin Max Unit Read Cycle Write CycleSwitching Waveforms Read Cycle 1 Address Transition Controlled18Read Cycle No OE Controlled19 Write Cycle No WE Controlled17, 21 Write Cycle No CE Controlled17, 21Data I/O Write Cycle No WE Controlled, OE LOW22 Write Cycle No BHE/BLE Controlled, OE LOW22DATAI/O Data Inputs/Outputs Mode Power Ordering InformationBHE BLE Package Diagram Ball Vfbga 6 x 8 x 1 mmPin Tsop II Issue Date Orig. Description of Change Document HistoryREV ECN no