Motorola MVME6100 manual Processor, L3 Cache, System Controller

Chapter 4 Functional Description

Processor

The MVME6100 supports the MPC7457 with adjustable core voltage supply. The maximum external processor bus speed is 133 MHz. The processor core frequency runs at 1.267 GHz or the highest speed MPC7457 can support, which is determined by the processor core voltage, the external speed, and the internal VCO frequency. MPX bus protocols are supported on the board. The MPC7457 has integrated L1 and L2 caches (as the factory build configuration) and supports an L3 cache interface with on-chip tags to support up to 2MB of off-chip cache. +2.5V signal levels are used on the processor bus.

L3 Cache

The MVME6100 external L3 cache is implemented using two 8Mb DDR SRAM devices. The L3 cache bus is 72-bits wide (64 bits of data and 8 bits of parity) and operates at 211 MHz. The L3 cache interface is implemented with an on-chip, 8-way, set-associative tag memory. The external SRAMs are accessed through a dedicated L3 cache port that supports one bank of SRAM. The L3 cache normally operates in copyback mode and supports system cache coherency through snooping. Parity generation and checking may be disabled by programming the L3CR register. Refer to the PowerPC Apollo Microprocessor Implementation Definition Book IV listed in Appendix C, Related Documentation.

System Controller

The MV64360 is an integrated system controller for high performance embedded control applications. The following features of the MV64360 are supported by the MVME6100:

The MV64360 has a five-bus architecture comprised of:

■A 72-bit interface to the CPU bus (includes parity)

■A 72-bit interface to DDR SDRAM (double data rate-synchronous DRAM) with ECC

■A 32-bit interface to devices

■Two 64-bit PCI/PCI-X interfaces

In addition to the above, the MV64360 integrates:

■Three Gigabit Ethernet MACs (only two are used on the MVME6100)

■2Mb SRAM

■Interrupt controller

■Four general-purpose 32-bit timers/counters

■I2C interface

■Four channel independent DMA controller

MVME6100 Installation and Use (V6100A/IH2) 37