Motorola MVME6100 manual Real-Time Clock/NVRAM/Watchdog Timer, Idsel Routing, Reset Control Logic

Chapter 4 Functional Description

Note On either PMC site, the user I/O – Jn4 signals will only support the low-current, high- speed signals and not for any current bearing power supply usage. The maximum current rating of each pin/signal is 250 mA.

Real-Time Clock/NVRAM/Watchdog Timer

The real-time clock/NVRAM/watchdog timer is implemented using an integrated SGS- Thompson M48T37V Timekeeper SRAM and Snaphat battery. The minimum M48T37V watchdog timer time-out resolution is 62.5 msec (1/16s) and maximum time-out period is 124 seconds. The interface for the Timekeeper and SRAM is connected to the MV64360 device controller bus on the MVME6100 board. Refer to the MV64360 Data Sheet, listed in Appendix C, Related Documentation, for additional information and programming details.

IDSEL Routing

PCI device configuration registers are accessed by using the IDSEL signal of each PCI agent to an A/D signal as defined in version 2.2 of the PCI specification. IDSEL assignments to on- board resources are specified in the MVME6100 Programmer’s Guide.

Reset Control Logic

The sources of reset on the MVME6100 are the following:

■Powerup

■Reset Switch

■NVRAM Watchdog Timer

■MV64360 Watchdog Timer

■VMEbus controller – Tsi148 ASIC

■System Control register bit

■PCI Bus 0 reset via System Control register

■PCI Bus 1 reset via System Control register

Debug Support

The MVME6100 provides JTAG/COP headers for debug capability for Processor as well as PCI0 bus use. These connectors are not populated as factory build configuration.

Processor JTAG/COP Headers

The MVME6100 provides JTAG/COP connectors for JTAG/COP emulator support (RISCWatch COP J42), as well as supporting board boundary scan capabilities (Boundary Scan header J8).

44MVME6100 Installation and Use (V6100A/IH2)