Agilent Technologies 66lxxA manual Status Byte Register, Output Queue, Location Of Event Handles

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Status Byte Register

This register summarizes the information from all other status groups as defined in the IEEE 488.2 Standard Digital Interface for Programmable Instrumentation standard. The bit configuration is shown in Table 4-2. The register can be read either by a serial poll or by *STB?. Both methods return the same data, except for bit 6. Sending *STB? returns MSS in bit 6, while polling returns RQS in bit 6.

The RQS Bit

Whenever the power module requests service, it sets the SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register. When the controller services the interrupt, RQS is cleared inside the register and returned in bit position 6 of the response. The remaining bits of the Status Byte register are not disturbed.

The MSS Bit

This is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the Service Request Enable register. MSS is set whenever the power module has at least one reason (and possible more) for requesting service. Sending *STB? reads the MSS in bit position 6 of the response. No bits of the Status Byte register are cleared by reading it.

Determining the Cause of a Service Interrupt

You can determine the reason for an SRQ by the following actions:

Use a serial poll or the *STB? query to determine which summary bits are active.

Read the corresponding Event register for each summary bit to determine which events caused the summary bit to be set. When an Event register is read, it is cleared. This also clears the corresponding summary bit.

The interrupt will recur until the specific condition that caused the each event is removed. If this is not possible, the event may be disabled by programming the corresponding bit of the status group Enable register or NTRPTR filter. A faster way to prevent the interrupt is to disable the service request by programming the appropriate bit of the Service Request Enable register.

Output Queue

The Output Queue is a first-in, first-out (FIFO) data register that stores power module-to-controller messages until the controller reads them. Whenever the queue holds one or more bytes, it sets the MAV bit (4) of the Status Byte register. If too many unread error messages are accumulated in the queue, a system error message is generated (see "Chapter 6 - Error Messages"). The Output Queue is cleared at power on and by *CLS.

Location Of Event Handles

"Event handles" are signals within the interface that can be used for triggers, for a Trigger Out signal, or for a DFI signal. Those event handles derived from signals in the Status Subsystem are shown as circled numbers in Figure 4-1. Other event handles are described in "Chapter 5 - Synchronizing Power Module Output Changes".

54 Status Reporting

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Contents Programming Guide Agilent Part No Microfiche Part No Update AprilSafety Guidelines Contents Abor Status Reporting Error Messages Synchronizing Power Module Output ChangesAbout This Guide IntroductionDocumentation Summary External ReferencesDownloading and Installing the Driver VXIplug&play Power Products Instrument DriversAccessing Online Help Supported ApplicationsIntroduction To Programming Gpib Capabilities Of The Power ModuleModule Gpib Address Introduction To ScpiRST *IDN? *SRE Voltlev 8.0 Prot 8.8 CURR? Volt LEV Prot CurrOutpprotdel Effect of Optional Headers Traversing the Command TreeOUTPUTPROTECTIONCLEARSTATUSOPERATIONCONDITION? Outputprotectionclear STATUSOPERATIONCONDITION?Voltagelevel 7PROTECTION 8CURRENTLEVEL 3MODE List Volttrig 7.5INIT*TRG Outp OFF*RCL 2OUTP onNumerical Data Formats Talking Formats SymbolListening Formats Suffixes and Multipliers Class Unit Unit with MultiplierAssign @PM3TO System ConsiderationsAgilent Basic Controllers Error HandlingUsing the National Instruments Gpib Interface Sending the Command Volt 5 in C Sending the Command Volt 5 in BasicReceiving Module Data with Basic Receiving Data from the ModuleReceiving Module Data with C Introduction Language DictionaryCLS Description Of Common CommandsMeaning and Type DescriptionESE Bit Configuration of Standard Event Status Enable RegisterESE ESR?OPC? IDN?OPC PSC OPT?RST RCLRCL SRE SAVSRE TRG Bit Configuration of Status Byte RegisterSTB? TST? Description of Subsystem CommandsWAI AborCalauto Subsystem Tree Diagram Calibration SubsystemCalcurr Calauto 1 Calauto OnceCalcurrlev CalpassCalstat CalsaveCalvolt CalvoltlevCurr CalvoltprotCurr 500 MA Currlev CurrmodeCurrprotstat OFF CurrprotstatCurrtrig Currtrig 1200 MA CurrlevtrigListcoun Init Initcont 1 Initcont onListcoun Listcoun INF ListcurrListdwel LISTCURRPOIN?LISTDWELPOIN? ListstepListvolt 2.0,2.5,3.0 Listvolt MAX,2.5,MIN ListvoltLISTVOLTPOIN? MEASCURR? MEASVOLT?Outpprot Outp Outpstat ON,NORELAYOutprel Outpprotcle Outpprotdel 75E-1Outprelpol NormOutpttlt 1 Outpttlt OFF OutpttltOutpttltlink Outpttltsour LinkSTATOPEREVEN? STATOPER?STATOPERCOND? StatoperenabStatpres Stat Oper NTR 32 Stat Oper PTRSTATQUESEVEN? STATQUES?STATQUESCOND? Stat Ques COND?SYSTVERS? SYSTERR?Trigger Subsystem TrigTrigdel Trig Trig IMMTrigdel .25 Trigdel MAX TriglinkVoltlev VoltVoltmode Voltmode List Voltmode FIXVolttrig 1200 MV Voltlevtrig VOLTSENSSOUR?Volttrig Link Parameter List Power Module Programming ParametersStatus Register Bit Configuration Power Module Status StructureStatus Reporting Operation Status GroupQuestionable Status Group Bit Signal Bit Configurations of Status Registers MeaningStatus Questionable Commands Query Standard Event Status Group Power Module Status ModelLocation Of Event Handles Status Byte RegisterOutput Queue Examples Initial Conditions At Power OnStatquesptr 18ENAB Statoperptr 5376ENABSTATOPEREVEN?QUESEVEN? Statoperptr 1024NTR Statoperenab 1024*SREModel of Fixed-Mode Trigger Operation Synchronizing Power Module Output ChangesTrigger Subsystem Initiated State Delaying StateIdle State INITiateCONTinuous Command Model of List Mode Trigger OperationTrigger Status and Event Signals Output Change StateOutpttltsour List Subsystem Automatically Repeating a List Listvolt 3.0,3.25,3.5,3.75 Listdwel 10,10,25,40Listcurr 2,3,12,15 Triggering a ListTiming diagrams of Liststep Operation RI Remote Inhibit Subsystem DFI Discrete Fault Indicator SubsystemScpi Command Completion Power Module Hardware Error Messages Error MessagesSystem Error Messages Standard Event Status Register Error Bits222 -223 -241 -310 -330 -350 -400 -410 -420 -430 Scpi Approved Commands Scpi Confirmed CommandsScpi Conformance Information Scpi VersionNon-SCPI Commands Application Programs Application 1. Sequencing Multiple Modules During Power Up Variations On This Implementation Figure B1-1. Block Diagram of Application #1Figure B1-2. Timing Diagram of Application #1 Enable Backplane TTL Trigger Drive Reset and Clear ModuleEnable Output Enable Response to TriggerImplementation Details How The MPS Implements The Solution MPS Set Up Figure B2-1. Block Diagram of Application #2 Enable TTL Trigger Drive When a CV-TO-CC Transition OccursEnable Response to TTL Trigger Start AT 15Application 3. Controlling Output Voltage Ramp Up at Turn On Figure B3-1. Simulating a Slow Voltage Ramp Generating the Desired Voltage Ramp for Application #3 Start Voltage for Ramp Option BaseStop Voltage for Ramp SecondsFigure B4-1. Voltage Waveform for Application #4 Application 4. Providing Time-Varying VoltagesModule set up Variations On This Implementation No Delay Before Protection Occurs Enable OCPEnable Detection of OC Condition Enables Detection on Positive TRANSITION, I.EApplication 5. Providing Time-Varying Current Limiting Figure B5-1. Typical DUT Current vs. Time Implementation Details How The MPS Implements The Sequence Current Limit Data GO to 12 V When TriggeredDwell Time Data SET to GET Current from ListNominal 12 Application 6. Output Sequencing Paced by the ComputerMPS Set Up Figure B6-1. Block Diagram of Application #6 Supply Limit Conditions These are the BiasTo be Tested Number of Bias Supply Limit C0MBINATIONSReturn Overview Of Application Advantages/Benefits Of The MPS Solution Figure B7-1. Block Diagram of Application #7 When IT Completes the LIST. OPC Generates SRO When the Module Indicates SIC Step CompletedEnable SRQ Interrupt Enable Intr Identify Handler SubroutineSupplemental Information CMD$ = Initiate ‘ Enable Trigger to Start List CMD$ = Output on ‘ Enable Output‘ Conversion to Send Real Numbers Over the BUS CMD$ = Voltmode List ‘ SET to GET Voltage from ListWaiting for Trigger BIT 5 of the Operation Status Register Call Iooutputs SLOTO, CMDS, LCONDITION.DATA = WendIf IBSTA% 0 then Goto ‘ AS Part of the Command String ‘ Disable Auto Serial Poll‘ Program N3.BAS ‘ INSTRUMENT.NAME$ = SlotoStop ‘ General Error HandlerIf IBSTA% 0 then Goto Selected AS a Trigger Source Dwell = ramptime Application #3 Controlling Voltage Ramp UP AT Turn onTo terminate the iooutputa Int error Char *badstring If error != EOl enabled for both read and write Strcatvlist, vpoint This is a generalized error checking routine Index IndexIndex Index Index United States Latin America Agilent Sales and Support OfficesManual Updates