Your ePlatform Partner
User’s Manual for Advantech
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| pole input pin. |
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90 | nRESET | I | System hardware reset input pin. | Pull high with | |
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| Falling edge triggered. Hard reset. | 10Kohm | |
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| (input) Level sensitive input used |
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| to start the processor from a known |
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| address. Assertion causes the |
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| current instruction to terminate |
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| abnormally and causes a reset. |
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| When nRESET is driven high, the |
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| processor starts execution from |
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| address 0. nRESET must remain |
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| low until the power supply is stable |
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| and the internal 3.6864 MHz |
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| oscillator has stabilized. |
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91 | nDC_IN | I | System DC input indicator pin. | Pull low with | |
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| When the pin is low, it means | 1Kohm | |
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| system is powered by external DC |
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| power source. If user target device |
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| is not power by battery, use could |
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| use this pin as GPIO. The pin |
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| connects to SoC PXA255 GPIO16. |
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92 | SYS_VCC | P | SOM system DC power 5V input | - | |
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| pin. SYS_VCC should always be |
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| powered by DC 5V even in sleep |
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| mode. |
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93 | SYS_VCC3P3 | P | SOM system DC power 3.3V input | - | |
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| pin. SYS_VCC should always be |
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| powered by DC 3.3V even in sleep |
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| mode. |
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94 | SYS_VCC | P | SOM system DC power 5V input | - | |
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| pin. SYS_VCC should always be |
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| powered by DC 5V even in sleep |
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| mode. |
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95 | SYS_VCC3P3 | P | SOM system DC power 3.3V input | - | |
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| pin. SYS_VCC should always be |
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| powered by DC 3.3V even in sleep |
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| mode. |
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96 | SMBUS_CLK | IO | System | Management Bus clock | Pull high with |
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| pin. The | pin is implemented by | 4.7Kohm |
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| SoC PXA255 I2C bus. |
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97 | SYS_VCC3P3 | P | SOM system DC power 3.3V input | - | |
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| pin. SYS_VCC should always be |
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| powered by DC 3.3V even in sleep |
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| mode. |
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98 | SMBUS_DAT | IO | System Management Bus data pin. | Pull high with | |
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| The pin is implemented by SoC | 4.7Kohm | |
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| PXA255 I2C bus. |
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99 | SYS_VCC3P3 | P | SOM system DC power 3.3V input | - | |
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| pin. SYS_VCC should always be |
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| powered by DC 3.3V even in sleep |
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