Advantech SOM-A2552 manual SASKT0VCC, Pwren, Batvcc

Page 19

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User’s Manual for Advantech SOM-A2552 series module V1.00

 

2

 

2.

 

79

nSA_SKT0_IOI

I

IO Select 16. (input) Acknowledge

Pull high with

 

S16

 

from the PCMCIA card that the

10Kohm

 

 

 

current address is a valid 16 bit

 

 

 

 

wide I/O address.

 

80

SA_SKT0_VCC

P

PCMCIA/CF slot 0 power pin.

Powered

81

nSA_SKT1_IOI

I

PCMCIA/CF slot 0 IO Select 16.

Pull high with

 

S16

 

Acknowledge from the PCMCIA

10Kohm

 

 

 

card that the current address is a

 

 

 

 

valid 16 bit wide I/O address.

 

82

nSA_PWR_ON

I

System suspend/wakeup input pin.

Pull high with

 

 

 

Falling edge triggered.

10Kohm

83

nBATT_FALT

I

Main Battery Fault. Signals that

Pull high with

 

 

 

main battery is low or removed.

100Kohm

 

 

 

Assertion causes PXA255

 

 

 

 

processor to enter sleep mode or

 

 

 

 

force an Imprecise Data Exception,

 

 

 

 

which cannot be masked. PXA255

 

 

 

 

processor will not recognize a

 

 

 

 

wakeup event while this signal is

 

 

 

 

asserted. Minimum assertion time

 

 

 

 

for nBATT_FAULT is 1 ms.

 

84

nSW_RESET

I

System software reset input pin.

Pull high with

 

 

 

Falling edge triggered.

10Kohm

85

nVDD_FALT

I

VDD Fault. Signals that the main

Pull high with

 

 

 

power source is going out of

100Kohm

 

 

 

regulation. nVDD_FAULT causes

 

 

 

 

the PXA255 processor to enter

 

 

 

 

sleep mode or force an Imprecise

 

 

 

 

Data Exception, which cannot be

 

 

 

 

masked. nVDD_FAULT is ignored

 

 

 

 

after a wakeup event until the

 

 

 

 

power supply timer completes

 

 

 

 

(approximately 10 ms). Minimum

 

 

 

 

assertion time for nVDD_FAULT is

 

 

 

 

1 ms.

 

86

nRESET_OUT

O

Reset Out. Asserted when

No pulling

 

 

 

nRESET is asserted and deasserts

 

 

 

 

after nRESET is deasserted but

 

 

 

 

before the first instruction fetch.

 

 

 

 

nRESET_OUT is also asserted for

 

 

 

 

“soft” reset events: sleep,

 

 

 

 

watchdog reset, or GPIO reset.

 

87

GND

P

Ground

-

88

PWR_EN

 

Power Enable for the power

Pull high with

 

 

O

supply. (output) When negated, it

100Kohm

 

 

 

signals the power supply to

 

 

 

 

remove power to the core because

 

 

 

 

the system is entering sleep mode.

 

89

BAT_VCC

P

3.0V li-ion coin battery positive

No pulling

19

Image 19
Contents Advantech Risc SOM-A2552 Series Module User’s ManualAcknowledgements CopyrightRevision History Version Date Reason SOM-A200 architecture SOM-A2552 series Architecture 1.1 IntroductionSOM-A2552 series Design highlight SOM-A2552 benefit Software Development Tools Testing SetSOM-A2552 series design-in package SOM-A255x series support CD includesLCD-A104-TTS1-0 Optional item Risc CE-BuilderLCD-A057-STQ1-0 Optional item LCD-A064-TTV1-0 Optional itemSOM-A2552 Block diagram Enhance Graphic Chip SMI SM501 introduction SoC Intel XScale PXA255 introductionSystem Memory Cpld System SpecificationsAudio Codec Mechanical Specification Input DC Operating Conditions Power System RequirementPower Consumption Symbol Description Min Typ MaxAssignments and Descriptions Connector LocationsX1 AMI bus CSB Mating Connector table VendorX2 SODIMM-200 connector X3 Feature Extension connectorPin type Pin DefinitionSODIMM-200 Pin Out Table JP1 PXA255 Jtag pin headerSASKTA4 SASKTA9SASKTA6 SASKTA7SASKT1RDY AC97LINEINMicin SASKT1VCCPwren SASKT0VCCBatvcc Smbusdat NDCINSysvcc SYSVCC3P3UART2RTS UsbcpBuzzerout USBLINK5VUART3CTS UART2CTSUART3TXD UART2DTRUART5RXD VbkenaUSBN1 USBP1Flmvsync VconrcsCrtvsync CrtsdaLphsync ADDR12 ADDR15ADDR14 ADDR13Bufsdclk BUFDQM0BUFDQM2 BUFDQM3DATA0 ADDR19ADDR21 ADDR23LAN1IRQ KeypadirqPXAGP7 EvairqPXAGP84 PXAGP81PXAGP82 PXAGP83Mbreq DMAREQ1DMAACK1 A50 3M6864 Model Default stateB50 MbgntA20 A18ZV8 MMDAT3MMDAT0 ZV9ZV3 ZV6ZV5 ZV4Vpclk System Bus2 COM A507 SD/MMC USB 1.1 HostUSB 1.1 client 5 T/SCRT-out Zoom Video ZV port System Reset InterfaceBuzzer Control Interface PCI I/F Thru Power-inputBack-up power input System Management Bus SM Bus interface