Chapter 3 | Hardware |
PC/104-Plus Interface (J21)
The
Table
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Table |
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| Pin # | Signal | Input/ | Description |
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| Output |
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| 1 (A1) | Key |
| Key pin (Not connected) |
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| 2 (A2) | VI/O |
| +5 volts ±5% power supply |
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| 3 (A3) | AD05 | T/S | PCI Address and Data Bus Line 5 – There are 32 signal lines |
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| (address and data) and the signals on these lines are multiplexed. A |
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| bus transaction consists of an address followed by one or more data |
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| cycles. |
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| 4 (A4) | C/BE0* | T/S | PCI Bus Command/Byte Enable 0 – This signal line is one of four |
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| signal lines. These signal lines are multiplexed, so that during the |
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| address cycle, the command is defined and during the data cycle, |
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| the byte enable is defined. |
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| 5 (A5) | GND |
| Ground |
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| 6 (A6) | AD11 | T/S | PCI Address and Data Bus Line 11 – Refer to Pin 3 for more |
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| information. |
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| 7 (A7) | AD14 | T/S | PCI Address and Data Bus Line 14 – Refer to Pin 3 for more |
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| information. |
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| 8 (A8) | +3.3V |
| +3.3 volts ±5% power supply |
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| 9 (A9) | SERR* | O/D | System Error – This signal is for reporting address parity errors. |
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| 10 (A10) | GND |
| Ground |
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| 11 (A11) | STOP* | S/T/S | Stop – This signal indicates the current selected device is |
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| requesting the master to stop the current transaction |
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| 12 (A12) | +3.3V |
| +3.3 volts ±5% power supply |
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| 13 (A13) | FRAME* | S/T/S | PCI bus Frame access – This signal is driven by the current master |
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| to indicate the start of a transaction and will remain active until the |
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| final data cycle |
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| 14 (A14) | GND |
| Ground |
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| 15 (A15) | AD18 | T/S | PCI Address and Data Bus Line 18 – Refer to Pin 3 for more |
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| information. |
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| 16 (A16) | AD21 | T/S | PCI Address and Data Bus Line 21 – Refer to Pin 3 for more |
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| information. |
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| 17 (A17) | +3.3V |
| +3.3 volts ±5% power supply |
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LittleBoard 550 | Reference Manual | 25 |